AD9778 Analog Devices, AD9778 Datasheet
AD9778
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AD9778 Summary of contents
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... Trademarks and registered trademarks are the property of their respective owners. 1 GSPS, Digital-to-Analog Converters AD9776/AD9778/AD9779 GENERAL DESCRIPTION The AD9776/AD9778/AD9779 are dual, 12-/14-/16-bit, high dynamic range, digital-to-analog converters (DACs) that pro- vide a sample rate of 1 GSPS, permitting multicarrier generation up to the Nyquist frequency. They include features optimized for direct conversion transmit applications, including complex digital modulation, and gain and offset compensation ...
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... AD9776/AD9778/AD9779 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Typical Signal Chain......................................................................... 1 Revision History ............................................................................... 2 Functional Block Diagram .............................................................. 3 Specifications..................................................................................... 4 DC Specifications ......................................................................... 4 Digital Specifications ................................................................... 6 Digital Input Data Timing Specifications ................................. 7 AC Specifications.......................................................................... 7 Absolute Maximum Ratings............................................................ 8 Thermal Resistance ...................................................................... 8 ESD Caution.................................................................................. 8 Pin Configurations and Function Descriptions ........................... 9 Typical Performance Characteristics ...
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... DAC ... 7 2× 2× 2× DIGITAL CONTROLLER SERIAL POWER-ON PERIPHERAL RESET INTERFACE Figure 2. Functional Block Diagram Rev Page AD9776/AD9778/AD9779 CLOCK CLK+ MULTIPLIER 2×/4×/8× CLK– 1 SYNC IOUT1_P 16-BIT IDAC IOUT1_N IOUT2_P 16-BIT QDAC IOUT2_N ...
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... AD9776/AD9778/AD9779 SPECIFICATIONS DC SPECIFICATIONS AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 =1.8 V, MIN MAX otherwise noted. Table 1. AD9776, AD9778, and AD9779 DC Specifications Parameter Min RESOLUTION ACCURACY Differential Nonlinearity (DNL) Integral Nonlinearity (INL) MAIN DAC OUTPUTS Offset Error −0.001 Gain Error (with Internal Reference) Full-Scale Output Current 1 8 ...
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... Power Supply Rejection Ratio, −0.3 AVDD33 OPERATING RANGE −40 1 Based kΩ external resistor. AD9776 AD9778 Typ Max Min Typ 980 980 2 3.7 2 +0.3 −0.3 +25 +85 −40 +25 Rev Page AD9776/AD9778/AD9779 AD9779 Max Min Typ Max 980 3.7 2 3.7 +0.3 −0.3 +0.3 +85 −40 +25 +85 Unit FSR/V °C ...
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... DIGITAL SPECIFICATIONS AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, MIN MAX otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted. Table 2. AD9776, AD9778, and AD9779 Digital Specifications Parameter CMOS INPUT LOGIC LEVEL Input V Logic High IN Input V ...
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... DIGITAL INPUT DATA TIMING SPECIFICATIONS Table 3. AD9776, AD9778, and AD9779 Digital Input Data Timing Specifications Parameter INPUT DATA (ALL MODES, −40°C to +85°C) Set-Up Time, Input Data to DATACLK Hold Time, Input Data to DATACLK Set-Up Time, Input Data to REFCLK Hold Time, Input Data to REFCLK 1 Timing vs ...
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... AD9776/AD9778/AD9779 ABSOLUTE MAXIMUM RATINGS Table 5. With Respect Parameter To Rating AVDD33, DVDD33 AGND, −0 +3.6 V DGND, CGND DVDD18, CVDD18 AGND, −0 +1.98 V DGND, CGND AGND DGND, −0 +0.3 V CGND DGND −0 +0.3 V AGND, CGND CGND AGND, −0 +0.3 V DGND I120, VREF, IPTAT AGND − ...
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... DVDD18 24 P1D<6> 25 P1D<5> 26 P1D<4> 27 P1D<3> 28 P1D<2> 29 P1D<1> 30 P1D<0> DGND 33 DVDD18 DATACLK 38 DVDD33 Rev Page AD9776/AD9778/AD9779 75 I120 74 VREF IPTAT 73 AGND 72 71 IRQ 70 RESET CSB 69 SCLK 68 SDIO 67 66 SDO 65 PLL_LOCK DGND 64 63 SYNC_O+ 62 SYNC_O– 61 DVDD33 DVDD18 60 NC ...
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... AD9776/AD9778/AD9779 Pin No. Mnemonic Description 39 TXENABLE Transmit Enable. 40 P2D<11> Port 2, Data Input D11 (MSB). 41 P2D<10> Port 2, Data Input D10. 42 P2D<9> Port 2, Data Input D9. 43 DVDD18 1.8 V Digital Supply. 44 DGND Digital Common. 45 P2D<8> Port 2, Data Input D8. 46 P2D<7> Port 2, Data Input D7. 47 P2D<6> Port 2, Data Input D6. ...
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... P1D<11> 19 P1D<10> 20 P1D<9> 21 DGND 22 DVDD18 23 P1D<8> 24 P1D<7> CONNECT Table 7. AD9778 Pin Function Description Pin No. Mnemonic Description 1 CVDD18 1.8 V Clock Supply. 2 CVDD18 1.8 V Clock Supply. 3 CGND Clock Common. 4 CGND Clock Common. ...
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... AD9776/AD9778/AD9779 Pin No. Mnemonic Description 41 P2D<12> Port 2, Data Input D12. 42 P2D<11> Port 2, Data Input D11. 43 DVDD18 1.8 V Digital Supply. 44 DGND Digital Common. 45 P2D<10> Port 2, Data Input D10. 46 P2D<9> Port 2, Data Input D9. 47 P2D<8> Port 2, Data Input D8. 48 P2D<7> Port 2, Data Input D7. 49 P2D<6> ...
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... P1D<8> 27 P1D<7> 28 P1D<6> 29 P1D<5> 30 P1D<4> 31 P1D<3> 32 DGND 33 DVDD18 34 P1D<2> 35 P1D<1> 36 P1D<0> 37 DATACLK 38 DVDD33 39 TXENABLE 40 P2D<15> 41 P2D<14> 42 P2D<13> Rev Page AD9776/AD9778/AD9779 75 I120 VREF 74 73 IPTAT 72 AGND IRQ 71 RESET 70 CSB 69 SCLK 68 SDIO 67 SDO 66 PLL_LOCK 65 64 DGND 63 SYNC_O+ 62 SYNC_O– DVDD33 61 DVDD18 60 59 P2D< ...
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... AD9776/AD9778/AD9779 Pin No. Mnemonic Description 43 DVDD18 1.8 V Digital Supply. 44 DGND Digital Common. 45 P2D<12> Port 2, Data Input D12. 46 P2D<11> Port 2, Data Input D11. 47 P2D<10> Port 2, Data Input D10. 48 P2D<9> Port 2, Data Input D9. 49 P2D<8> Port 2, Data Input D8. 50 P2D<7> Port 2, Data Input D7. 51 P2D<6> ...
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... OUT Figure 8. AD9779 In-Band SFDR vs. f OUT 50k 60k 50k 60k f = 250MSPS DATA = 200MSPS 80 100 , 1x Interpolation Rev Page AD9776/AD9778/AD9779 100 f = 160MSPS DATA 200MSPS DATA 250MSPS DATA (MHz) OUT Figure 9. AD9779 In-Band SFDR vs 2× ...
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... AD9776/AD9778/AD9779 100 160MSPS DATA 200MSPS DATA (MHz) OUT Figure 12. AD9779 Out-of-Band SFDR vs. f 100 150MSPS DATA 100MSPS DATA 60 f DATA (MHz) OUT Figure 13. AD9779 Out-of-Band SFDR vs. f 100 ...
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... Figure 22. AD9779 Third-Order IMD vs. f 100 320 360 400 0 Figure 23. AD9779 Third-Order IMD vs. f Rev Page AD9776/AD9778/AD9779 f = 75MSPS DATA f = 100MSPS DATA f = 50MSPS DATA f = 125MSPS DATA f (MHz) OUT , 8× Interpolation OUT PLL OFF PLL ON 20 ...
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... AD9776/AD9778/AD9779 100 95 90 0dBFS 85 –3dBFS 80 75 –6dBFS 120 160 200 240 f (MHz) OUT Figure 24. IMD Performance vs. Digital Full-Scale Input, 4× Interpolation 200 MSPS DATA 100 95 90 20mA 85 10mA 80 75 30mA 120 160 200 ...
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... DAC Interpolation, f 0dBFS – PLL ON –6dBFS 260 Figure 33. AD9779 ACLR for Third Adjacent Band WCDMA, 4× Interpolation 122.88 MSPS, On-Chip Modulation Translates Baseband Signal to IF DATA Rev Page AD9776/AD9778/AD9779 –55 –60 –65 –70 0dBFS – PLL ON –75 –6dBFS –80 –85 0dBFS – ...
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... EXT REF SPAN 50MHz UPPER dBc dBm –67.70 –85.57 –69.32 –87.19 –71.00 –88.88 Rev Page 1.5 1.0 0 CODE Figure 36. AD9778 Typical INL 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 10k 12k CODE Figure 37. AD9778 Typical DNL 8k 10k 14k 16k ...
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... CARRIER POWER –12.74dBm/ 3.84000MHz Figure 41. AD9778 ACLR, f –150 –154 = 200MSPS –158 –162 –166 –170 80 100 0 Figure 42. AD9778 Noise Spectral Density vs. f –150 –154 –158 –162 –166 –170 200 225 250 0 Figure 43. AD9778 Noise Spectral Density vs. f Rev Page AD9776/AD9778/AD9779 ...
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... AD9776/AD9778/AD9779 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 0 512 1024 1536 2048 2560 CODE Figure 44. AD9776 Typical INL 0.20 0.15 0.10 0.05 0 –0.05 –0.10 –0.15 –0.20 0 512 1024 1536 2048 2560 CODE Figure 45. AD9776 Typical DNL 100 4× 100MSPS 4× 150MSPS ...
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... OUT Figure 50. AD9776 Noise Spectral Density vs. f DAC with 500 kHz Spacing 200 MSPS DATA –150 –154 –158 –162 –166 80 90 100 –170 0 , Eight-Tone Input Rev Page AD9776/AD9778/AD9779 f = 200MSPS DAC f = 400MSPS DAC f = 800MSPS DAC (MHz) OUT Figure 51 ...
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... AD9776/AD9778/AD9779 TERMINOLOGY Integral Nonlinearity (INL) INL is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. ...
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... Motorola SPI and Intel SSR protocols. The interface allows read/write access to all registers that configure the AD9776/ AD9778/AD9779. Single or multiple byte transfers are sup- AD9776/AD9778/AD9779 ported, as well as MSB-first or LSB-first transfer formats. The serial interface ports can be configured as a single pin I/O (SDIO) or two unidirectional pins for input/output (SDIO/SDO) ...
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... AD9776/AD9778/AD9779 For multibyte transfers, this address is the starting byte address. The remaining register addresses are generated by the device based on the LSB-first bit (Register 0x00, Bit 6). Table 10. Byte Transfer Count N1 N0 Description 0 0 Transfer one byte 0 1 Transfer three bytes 1 0 Transfer two bytes ...
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... Q DAC Gain Adjustment<7:0> Q DAC Power- Down Auxiliary DAC2 Data<7:0> Auxiliary DAC2 Auxiliary Current Direction DAC2 Power- Down Reserved Sync Delay IRQ Reserved Rev Page AD9776/AD9778/AD9779 Bit 3 Bit 2 Bit 1 Bit 0 Auto PLL Lock Power- Indicator Down (Read Enable Only) Zero Stuffing ...
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... AD9776/AD9778/AD9779 Table 12. SPI Register Description Address Register Name Reg. No. Bits Comm Register Digital Control Register 01 7 Sync Control Register 03 7:6 03 5:4 03 3:0 04 7 7 Description Function ...
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... Aux DAC1 power-down 0: Aux DAC1 on 1: Aux DAC1 off Aux DAC1 gain adjustment (9:8) MSB slice of 10-bit gain setting word for Aux DAC1 Rev Page AD9776/AD9778/AD9779 DAC 00 × × × × REF 00 × × × ...
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... AD9776/AD9778/AD9779 Address Register Name Reg. No. Bits Q DAC Control Register 0F 7 1:0 Aux DAC2 Control 11 7:0 Register 1:0 Interrupt Register Description Function Q DAC gain adjustment (7:0) LSB slice of 10-bit gain setting word for Q DAC ...
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... INTERPOLATION FILTER ARCHITECTURE The AD9776/AD9778/AD9779 can provide up to 8× interpola- tion, or the interpolation filters can be entirely disabled important to note that the input signal should be backed off by approximately 0.01 dB from full scale to avoid overflowing the interpolation filters. The coefficients of the low-pass filters and the inverse sinc filter are given in Table 13, Table 14, Table 15, and Table 16 ...
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... AD9776/AD9778/AD9779 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –4 –3 –2 – (× Input Data Rate) OUT Figure 59. 8× Interpolation, Low-Pass Response to ±4× Input Data Rate (Dotted Lines Indicate 1 dB Roll-Off) With the interpolation filter and modulator combined, the incoming signal can be placed anywhere within the Nyquist region of the DAC output sample rate ...
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... The shifted mode capability allows the filter pass band to be placed anywhere in the DAC Nyquist bandwidth. The AD9776/AD9778/AD9779 are dual DACs with internal complex modulators built into the interpolating filter response. ...
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... AD9776/AD9778/AD9779 Table 17. Interpolation Filter Modes, (Register 0x01, Bits<5:2>) Filter Interpolation Mode Factor <7:6> <5:2> Modulation 8 0x00 DC 8 0x01 DC shifted 8 0x02 F/8 8 0x03 F/8 shifted 8 0x04 F/4 8 0x05 F/4 shifted 8 0x06 3F/8 8 0x07 3F/8 shifted 8 0x08 F/2 8 0x09 F/2 shifted 8 0x0A −3F/8 8 0x0B −3F/8 shifted 8 0x0C −F/4 8 0x0D −F/4 shifted 8 0x0E −F/8 ...
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... V p-p about the 400 mV common-mode voltage. While these input levels are not directly LVDS-compatible, REFCLK can be driven by an offset ac-coupled LVDS signal, as shown in Figure 71 Rev Page AD9776/AD9778/AD9779 10 0 –10 –20 –30 –40 –50 –60 – ...
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... AD9776/AD9778/AD9779 0.1μF LVDS_P_IN 50Ω 50Ω LVDS_N_IN 0.1μF Figure 71. LVDS REFCLK Drive Circuit If a clean sine clock is available, it can be transformer-coupled to REFCLK, as shown in Figure 71. Use of a CMOS or TTL clock is also acceptable for lower sample rates. It can be routed through a CMOS to LVDS translator, then ac-coupled, as described in this section ...
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... For optimal performance, the bandwidth adjustment 1170 1204 (Register 0x0A, Bits<4:0>) should be set to 11111 for all 1159 1189 operating modes with PLL enabled. The PLL bias settings Rev Page AD9776/AD9778/AD9779 Typical PLL Lock Ranges VCO Frequency Range in MHz Typ at 25°C Typ over Temp ...
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... AD9776/AD9778/AD9779 (Register 0x09, Bits<2:0>) should be set to 111. The PLL control voltage (Register 0x0A, Bits<7:5>) is read back and is propor- tional to the dc voltage at the internal loop filter output. With the PLL bias settings given in this section, the readback from the PLL control voltage should typically be 010, or possibly 001 or 011 ...
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... PASSIVE Q INPUTS Figure 82. Power Dissipation, Digital 1.8 V Supply, I Data Only, Real Mode, QUAD MOD INPUTS 25Ω TO 50Ω Figure 83. Power Dissipation, Clock 1.8 V Supply, I Data Only, Real Mode, Rev Page AD9776/AD9778/AD9779 0.7 8 × INTERPOLATION 0.6 4 × INTERPOLATION 4 × INTERPOLATION, 8 × INTERPOLATION, ZERO STUFFING ...
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... AD9776/AD9778/AD9779 0.075 ALL INTERPOLATION MODES 0.050 0.025 100 125 150 f (MSPS) DATA Figure 84. Digital 3.3 V Supply, I Data Only, Real Mode, Includes Modulation Modes and Zero Stuffing 1.0 8× INTERPOLATION, ALL MODULATION MODES 8× INTERPOLATION, 0.9 ZERO STUFFING 0.8 0.7 0.6 0.5 0.4 0.3 2× INTERPOLATION, 0.2 ZERO STUFFING 4× INTERPOLATION, 1× ...
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... Figure 92 to Figure 95 recommended that any toggling of TXENABLE occur concurrently with the digital data input updating. In this way, timing margins between DATACLK, TXENABLE, and digital input data are optimized. Rev Page AD9776/AD9778/AD9779 FLUSHING ...
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... AD9776/AD9778/AD9779 REFERENCE CLOCK IN CLOCK OUT Figure 92. Timing Specifications, PLL Enabled or Disabled, Interpolation = 1× SYNC_IN REFERENCE CLOCK IN DATA CLOCK OUT INPUT DATA Figure 93. Timing Specifications, PLL Enabled or Disabled, Interpolation = 2× SYNC_IN REFERENCE CLOCK IN DATA CLOCK OUT INPUT DATA Figure 94. Timing Specifications, PLL Enabled or Disabled, Interpolation = 4× ...
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... REFCLK and SYNC_I (see Table 19 for timing relationship being an integer DAC_SAMPLE t DAC_SAMPLE Figure 96. Valid Timing Relationship for SYNC_I to REFCLK Rev Page AD9776/AD9778/AD9779 and t requirements are S H and 1.0 ns, this gives a valid timing window ...
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... AD9776/AD9778/AD9779 Using Data Delay to Meet Timing Requirements To meet strict timing requirements at input data rates 250 MSPS, the AD977x has a fine timing feature. Fine timing adjustments are made by programming values into the data clock delay register (Register 0x04, Bits<7:4>). This register can be used to add delay between the REFCLK in and the DATACLK out ...
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... Reserved 10 Reserved 11 Reserved AD9776/AD9778/AD9779 Necessary corrections can be made by adjusting DATACLK delay and the DATACLK invert bit (Register 2, Bit 2). DATACLK delay can then be swept to find the range over which the timing is valid. The final value for data delay should be the value that corresponds to the middle of the valid timing range. ...
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... AD9776/AD9778/AD9779 EVALUATION BOARD OPERATION The AD977x evaluation board is designed to optimize the DAC performance and the speed of the digital interface, yet remains user friendly. To operate the board, the user needs a power source, a clock source, and a digital data source. The user also needs a spectrum analyzer or an oscilloscope to look at the DAC output ...
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... MHz recommended that the transformer be placed right after the DAC. Above DAC output frequencies of 30 MHz recommended that the common-mode transformer is placed right after the DAC outputs, followed by the transformer. Rev Page AD9776/AD9778/AD9779 ...
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... AD9776/AD9778/AD9779 MODIFYING THE EVALUATION BOARD TO USE THE AD8349 ON-BOARD QUADRATURE MODULATOR The evaluation board contains an Analog Devices quadrature modulator. The AD977x and AD8349 provide an easy-to-interface DAC/modulator combination that can be easily evaluated on the evaluation board. To route the DAC output signal to the quadrature modulator, the following ...
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... EVALUATION BOARD SCHEMATICS Figure 104. Evaluation Board, Rev. D, Power Supply Decoupling and SPI Interface AD9776/AD9778/AD9779 Rev Page ...
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... AD9776/AD9778/AD9779 T2B T1B ADTL1-12 ADTL1-12 T2A T1A TC1-1T TC1-1T C62 C33 0.1µF 1nF JP4 D1P C61 C37 1nF 0.1µF C60 C24 0.1µF 1nF C9 C59 0.1µF 1nF C1 VOLT 4.7µF AVDD33 ...
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... DNB R29 R31 C17 0.1 μ Ω 300 Ω C23 ETC1-1-13 0.1 μ F Rev Page AD9776/AD9778/AD9779 C53 0.1µF R22 147.5Ω MODULATED OUTPUT C47 J4 100pF DGND2 DGND2 VDDM R14 1kΩ JP1 2 DGND2 LOCAL OSC OUTPUT ...
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... AD9776/AD9778/AD9779 A10 B10 A11 B11 A15 B15 A16 B16 A17 B17 A18 B18 A19 B19 A20 B20 A21 B21 A22 B22 A23 B23 A24 B24 A25 B25 PKG_TYPE = MOLEX110 PKG_TYPE = MOLEX110 ...
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... Figure 110. Evaluation Board, Rev. D, Top Silk Screen Figure 111. Evaluation Board, Rev. D, Top Layer Rev Page AD9776/AD9778/AD9779 ...
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... AD9776/AD9778/AD9779 Figure 112. Evaluation Board, Rev. D, Layer 2 Figure 113. Evaluation Board, Rev. D, Layer 3 Rev Page ...
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... Figure 114. Evaluation Board, Rev. D, Bottom Layer Figure 115. Evaluation Board, Rev. D, Bottom Silkscreen Rev Page AD9776/AD9778/AD9779 ...
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... AD9779BSVZ −40°C to +85°C 1 AD9779BSVZRL −40°C to +85°C AD9776-EB AD9778-EB 1 AD9779-EBZ RoHS Compliant Part. ©2005–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 16.00 BSC SQ 14.00 BSC SQ ...