CS8420-CSZ Cirrus Logic Inc, CS8420-CSZ Datasheet - Page 59

• Manufacturer Part Number: CS8420-CSZ
• Description: IC SAMPLE RATE CONVERTER 28SOIC
• Manufacturer: Cirrus Logic Inc
• Type: Sample Rate Converterr

Specifications of CS8420-CSZ

• Package / Case: 28-SOIC
• Applications: CD-R, DAT, DVD, MD, VTR
• Mounting Type: Surface Mount
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 10 C to + 70 C
• Mounting Style: SMD/SMT
• Resolution: 17 bit to 24 bit
• Control Interface: 3 Wire, Serial
• Supply Voltage Range: 4.75V To 5.25V
• Audio Ic Case Style: SOIC
• No. Of Pins: 28
• Bandwidth: 20kHz
• Rohs Compliant: Yes
• Audio Control Type: Volume
• Dc: 0841
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1782 - EVALUATION BOARD FOR CS8420
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1125-5

DS245F4
13.3
Hardware Mode 2 Description
(DEFAULT Data Flow, Serial Input)
Hardware Mode 2 data flow is shown in
rate converted. The audio data at the new rate is then output both via the serial audio output port and via
the AES3 transmitter.
The C, U, and V bits in the AES3 output stream may be set in two methods, selected by the CUVEN pin.
When CUVEN is low, mode 2A is selected, where COPY/C, ORIG/U, and EMPH/V pins allow selected
channel status data bits to be set. The COPY and ORIG pins are used to set the pro bit, the copy bit, and
the L bit, as shown in
indicates sample rate converter. The transmitted U and V bits are zero.When the CUVEN pin is high, mode
2B is selected, where COPY/C, ORIG/U, and EMPH/V become serial bit inputs for C, U, and V data. This
data is clocked by both edges of OLRCK, and the channel status block start is indicated or determined by
TCBL. Figure
Audio serial port data formats are selected as shown in Tables 6,
Start-up options are shown in
and whether TCBL is an input or an output. The serial audio input port is always a slave.
ILRCK
ISCLK
SDIN
RMCK
Power supply pins (VD+, VA+, DGND, AGND) & the reset pin (RST) and the PLL filter pin (FILT)
are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details.
20
Figure 25. Hardware Mode 2 - Default Data Flow, Serial Audio Input
shows the timing requirements.
Serial
Audio
Input
DFC0
LOCK
Table
SFMT1 SFMT0
9. In consumer mode, the transmitted category code shall be 0101100b, which
DFC1
Table
Clocked by
Input Derived Clock
11, and allow choice of the serial audio output port as a master or slave
VD+
S/AES
Figure
COPY/C ORIG/U EMPH/V CUVEN TCBL
Sample
Rate
Converter
VD+
25. Audio data is input via the serial audio input port, and
Clocked by
Output Clock
H/S
C & U bit Data Buffer
7
Output
Clock
Source
and 10.
AES3
Encoder
& Tx
Serial
Audio
Output
OMCK
TXP
TXN
OLRCK
OSCLK
SDOUT
CS8420
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