AD5363 Analog Devices, AD5363 Datasheet - Page 23

• Manufacturer Part Number: AD5363
• Description: 8-Channel, 14-Bit, Serial Input, Voltage-Output DAC
• Manufacturer: Analog Devices

Specifications of AD5363

• Resolution (bits): 14bit
• Dac Settling Time: 20µs
• Single-supply: No
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

PACKET ERROR CHECKING
To verify that data has been received correctly in noisy environ-
ments, the AD5362/AD5363 offer the option of error checking
based on an 8-bit (CRC-8) cyclic redundancy check. The device
controlling the AD5362/AD5363 should generate an 8-bit
checksum using the polynomial C(x) = x
added to the end of the data-word, and 32 data bits are sent to
the AD5362/AD5363 before taking SYNC high. If the AD5362/
AD5363 see a 32-bit data frame, an error check is performed
when SYNC goes high. If the checksum is valid, the data is
written to the selected register. If the checksum is invalid, the
packet error check ( PEC ) output goes low and Bit 3 of the
control register is set. After reading the control register, Bit 3
is cleared automatically and PEC goes high again.
Table 14. Group and Channel Addressing
Address Bit A2
to Address Bit A0
000
001
010
011
100
101
110
111
SYNC
SCLK
SYNC
SCLK
PEC
SDI
SDI
Figure 24. SPI Write With and Without Error Checking
MSB
MSB
D23
D31
24-BIT DATA TRANSFER—NO ERROR CHECKING
24-BIT DATA TRANSFER WITH ERROR CHECKING
24-BIT DATA
UPDATE ON SYNC HIGH
00
All groups, all channels
Group 0, all channels
Group 1, all channels
Unused
Unused
Unused
Unused
Unused
24-BIT DATA
UPDATE AFTER SYNC HIGH
ONLY IF ERROR CHECK PASSED
LSB
LSB
D0
D8
PEC GOES LOW IF
ERROR CHECK FAILS
8
+ x
D7
2
8-BIT FCS
+ x
1
+ 1. This is
D0
01
Group 0, Channel 0
Group 0, Channel 1
Group 0, Channel 2
Group 0, Channel 3
Unused
Unused
Unused
Unused
Rev. A | Page 23 of 28
Address Bit A4 to Address Bit A3
CHANNEL ADDRESSING AND SPECIAL MODES
If the mode bits are not 00, the data-word D15 to D0 (AD5362)
or D13 to D0 (AD5363) is written to the device. Address Bit A4
to Address Bit A0 determine which channels are written to, and
the mode bits determine to which register (X1A, X1B, C, or M)
the data is written, as shown in Table 13 and Table 14. Data is to
be written to the X1A register when the A /B bit in the control
register is 0, or to the X1B register when the A /B bit is 1.
The AD5362/AD5363 have very flexible addressing that allows
the writing of data to a single channel, all channels in a group,
or all channels in the device.
Table 14 shows which groups and which channels are addressed
for every combination of Address Bit A4 to Address Bit A0.
Table 13. Mode Bits
M1
1
1
0
0
M0
1
0
1
0
Write to DAC offset (C) register
Action
Write to DAC data (X) register
Write to DAC gain (M) register
Special function, used in combination with other
bits of the data-word
10
Group 1, Channel 0
Group 1, Channel 1
Group 1, Channel 2
Group 1, Channel 3
Unused
Unused
Unused
Unused
AD5362/AD5363
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
11