AD5363 Analog Devices, AD5363 Datasheet

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AD5363

Manufacturer Part Number
AD5363
Description
8-Channel, 14-Bit, Serial Input, Voltage-Output DAC
Manufacturer
Analog Devices
Datasheet

Specifications of AD5363

Resolution (bits)
14bit
Dac Settling Time
20µs
Single-supply
No
Dac Type
Voltage Out
Dac Input Format
Ser,SPI

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD5363BSTZ
Manufacturer:
ADI
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329
Part Number:
AD5363BSTZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
AD5363BSTZ-REEL
Manufacturer:
Analog Devices Inc
Quantity:
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FEATURES
8-channel DAC in 52-lead LQFP and 56-lead LFCSP packages
Guaranteed monotonic to 16/14 bits
Nominal output voltage range of −10 V to +10 V
Multiple output voltage spans available
Thermal shutdown function
Channel monitoring multiplexer
GPIO function
System calibration function allowing user-programmable
Channel grouping and addressing features
Data error checking feature
SPI-compatible serial interface
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
offset and gain
BIN/2SCOMP
TEMP_OUT
MON_OUT
MON_IN0
MON_IN1
RESET
SYNC
SCLK
BUSY
GPIO
SDO
PEC
CLR
SDI
AD5362/
MUX
AD5363
INTERFACE
REGISTER
REGISTER
CONTROL
MACHINE
SENSOR
SERIAL
STATE
TEMP
GPIO
VOUT0 TO
VOUT7
DV
CC
n
8
6
2
V
DD
8
8
n
n
n
n
n
n
n
n
n
n
n
n
n = 16 FOR AD5362
n = 14 FOR AD5363
V
X1 REGISTER
X1 REGISTER
X1 REGISTER
X1 REGISTER
M REGISTER
M REGISTER
C REGISTER
M REGISTER
M REGISTER
C REGISTER
C REGISTER
A/B SELECT
C REGISTER
A/B SELECT
SS
REGISTER
REGISTER
AGND DGND
·
·
·
·
·
·
n
n
n
n
n
n
n
n
n
8
n
n
n
8
·
·
·
·
·
·
FUNCTIONAL BLOCK DIAGRAM
·
·
·
·
·
·
TO
MUX 2s
TO
MUX 2s
n
n
n
n
A/B
MUX
A/B
MUX
A/B
MUX
A/B
MUX
·
·
·
·
·
·
X2A REGISTER
X2B REGISTER
X2A REGISTER
X2B REGISTER
X2A REGISTER
X2B REGISTER
X2A REGISTER
X2B REGISTER
·
·
·
·
·
·
Figure 1.
Serial Input, Voltage Output DAC
MUX
MUX
MUX
MUX
2
2
2
2
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
2.5 V to 5.5 V digital interface
Digital reset (RESET)
Clear function to user-defined SIGGNDx
Simultaneous update of DAC outputs
APPLICATIONS
Instrumentation
Industrial control systems
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical line cards
14
14
LDAC
n
n
n
n
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
DAC 0
DAC 4
DAC 7
DAC 3
OFS0
OFS1
·
·
·
·
·
·
·
14
n
n
n
n
n
8-Channel, 16-/14-Bit,
OFFSET
OFFSET
DAC 4
DAC 7
DAC 3
DAC 1
DAC 0
DAC 0
©2008 Analog Devices, Inc. All rights reserved.
BUFFER
BUFFER
·
·
·
·
·
·
AD5362/AD5363
BUFFER
BUFFER
OUTPUT BUFFER
DOWN CONTROL
OUTPUT BUFFER
DOWN CONTROL
OUTPUT BUFFER
DOWN CONTROL
OUTPUT BUFFER
DOWN CONTROL
AND POWER-
AND POWER-
AND POWER-
AND POWER-
GROUP 0
GROUP 1
·
·
·
·
·
·
www.analog.com
VOUT0
VOUT1
VOUT2
VOUT3
SIGGND0
VREF1
VOUT4
VOUT5
VOUT6
VOUT7
SIGGND1
VREF0

Related parts for AD5363

AD5363 Summary of contents

Page 1

... Channel grouping and addressing features Data error checking feature SPI-compatible serial interface AGND DGND TEMP TEMP_OUT SENSOR FOR AD5362 FOR AD5363 CONTROL PEC REGISTER VOUT0 TO 8 MON_IN0 A/B SELECT VOUT7 REGISTER 6 MON_IN1 MUX n X1 REGISTER n ...

Page 2

... AD5362/AD5363 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications ..................................................................................... 4 AC Characteristics ........................................................................ 6 Timing Characteristics ................................................................ 7 Absolute Maximum Ratings .......................................................... 10 ESD Caution ................................................................................ 10 Pin Configuration and Function Descriptions ........................... 11 Typical Performance Characteristics ........................................... 13 Terminology .................................................................................... 15 Theory of Operation ...................................................................... 16 DAC Architecture ....................................................................... 16 Channel Groups .......................................................................... 16 A/B Registers and Gain/Offset Adjustment ............................ 17 Offset DACs ...

Page 3

... V AD5379 14 ±8.75 V The AD5362/AD5363 have a high speed 4-wire serial interface that is compatible with SPI, QSPI™, MICROWIRE™, and DSP interface standards and can handle clock speeds MHz. All the outputs can be updated simultaneously by taking the LDAC input low. Each channel has a programmable gain and an offset adjust register ...

Page 4

... REF 1 B Version Unit Test Conditions/Comments 16 Bits AD5362 14 Bits AD5363 ±4 LSB max AD5362 ±1 LSB max AD5363 ±1 LSB max Guaranteed monotonic by design over temperature ±15 mV max Before calibration ±20 mV max Before calibration 0.1 % FSR Before calibration 1 LSB typ After calibration ...

Page 5

... Rev Page AD5362/AD5363 Test Conditions/Comments Sinking 200 μA Sourcing 200 μA SDO only @ 25°C −40°C < T < +85°C Current source only To within ±5° 5 ...

Page 6

... AD5362/AD5363 AC CHARACTERISTICS − offset (C), and DAC offset registers at default values; all specifications T Table 3. Parameter 1 DYNAMIC PERFORMANCE Output Voltage Settling Time Slew Rate Digital-to-Analog Glitch Energy Glitch Impulse Peak Amplitude Channel-to-Channel Isolation DAC-to-DAC Crosstalk ...

Page 7

... SCLK rising edge to SDO valid ns max RESET rising edge to BUSY falling edge ) and timed from a voltage level of 1 OUTPUT V OL Rev Page AD5362/AD5363 = 200 pF to GND unless otherwise noted. MIN MAX 200µ (MIN) – V (MAX) ...

Page 8

... AD5362/AD5363 SCLK SYNC 5 DB23 SDI BUSY 1 LDAC 1 VOUTx 2 LDAC 2 VOUTx CLR VOUTx RESET VOUTx BUSY 1 LDAC ACTIVE DURING BUSY. 2 LDAC ACTIVE AFTER BUSY DB0 Figure 4. SPI Write Timing Rev ...

Page 9

... DB15 SELECTED REGISTER DATA CLOCKED OUT Figure 5. SPI Read Timing FULL-SCALE ERROR + ZERO-SCALE ERROR ACTUAL TRANSFER FUNCTION IDEAL TRANSFER FUNCTION N DAC CODE 2 – FOR AD5362 FOR AD5363 ZERO-SCALE ERROR Figure 6. DAC Transfer Function Rev Page AD5362/AD5363 48 DB0 DB0 ...

Page 10

... AD5362/AD5363 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Transient currents not cause SCR latch-up. Table 5. Parameter V to AGND AGND DGND CC Digital Inputs to DGND Digital Outputs to DGND VREF0, VREF1 to AGND VOUT0 through VOUT7 to AGND SIGGND0, SIGGND1 to AGND ...

Page 11

... VREF0 Reference Input for DAC 0 to DAC 3. This reference voltage is referred to AGND. Rev Page AD5362/AD5363 RESET 1 2 PIN 1 BUSY 3 INDICATOR GPIO 4 5 AD5362/ MON_IN0 AD5363 TOP VIEW NC (Not to Scale VREF1 14 Figure 8. 56-Lead LFCSP Pin Configuration ...

Page 12

... AD5362/AD5363 Pin No. LQFP LFCSP 43, 51 45, 53 44 Exposed Paddle Mnemonic Description TEMP_OUT Provides an output voltage proportional to the chip temperature, typically 1. 25°C with an output variation of 4.4 mV/°C. SIGGND0 Reference Ground for DAC 0 to DAC 3. VOUT0 to VOUT3 are referenced to this voltage ...

Page 13

... + +3V REF 0.5 0 –0.5 –1 600 500 400 300 200 100 Rev Page AD5362/AD5363 TIME (µs) Figure 12. Digital Crosstalk 0 16384 32768 49152 DAC CODE Figure 13. Typical AD5362 DNL Plot FREQUENCY (Hz) Figure 14. Output Noise Spectral Density = 25° ...

Page 14

... AD5362/AD5363 0. –12V +12V +3V REF 0. +5.5V CC 0.40 0. +2.5V CC 0.30 0.25 –40 – TEMPERATURE (°C) Figure 15. DI vs. Temperature CC 6 6 –12V +12V +3V REF 4.5 –40 – TEMPERATURE (°C) Figure 16 vs. Temperature 5.8 6.0 6.2 I (mA) DD Figure 17. Typical I ...

Page 15

... It is specified as the area of the glitch in nV- measured by toggling the DAC register data between 0x7FFF and 0x8000 (AD5362) or 0x1FFF and 0x2000 (AD5363). Channel-to-Channel Isolation Channel-to-channel isolation refers to the proportion of input signal from one DAC reference input that appears at the output of another DAC operating from another reference ...

Page 16

... The resistor-string section is simply a string of resistors, of equal value, from VREF0 or VREF1 to AGND. This type of architecture guarantees DAC monotonicity. The 16-bit (AD5362) or 14-bit (AD5363) binary digital code loaded to the DAC register determines at which node on the string the voltage is Table 7. AD5362/AD5363 Registers ...

Page 17

... X2A or X2B register. A global command is also provided that sets all bits in the A/B select registers All DACs in the AD5362/AD5363 can be updated simultane- ously by taking LDAC low when each DAC register is updated from either its X2A or X2B register, depending on the setting of the A/B select registers ...

Page 18

... DAC. If the offset and gain features are not used (that is, the M and C registers are left at their default values), the required reference levels can be calculated as follows: VREF = (VOUT If the offset and gain features of the AD5362/AD5363 are used − 2 the required output range is slightly different. The selected output range should take into account the system offset and gain errors that need to be trimmed out ...

Page 19

... These limitations can be overcome by increasing the reference value. With a 2.5 V reference span is achieved. The ideal voltage range, for the AD5362 or the AD5363, is − Using a +2.6 V reference increases the range to −5 +5.2 V. Clearly, in this case, the offset and gain errors are insignificant, and the M and C registers can be used to raise the negative voltage to − ...

Page 20

... LDAC is brought low, the DAC registers are filled with the contents of the X2A or X2B registers, depending on the setting of the A/B select registers. However, the AD5362/ AD5363 update the DAC register only if the X2A or X2B data has changed, thereby removing unnecessary digital crosstalk. BIN/2SCOMP PIN The BIN /2SCOMP pin determines if the output data is presented as offset binary or twos complement ...

Page 21

... To indicate that the AD5362/AD5363 have entered thermal shutdown mode, Bit 4 of the control register is set to 1. The AD5362/AD5363 remain in thermal shutdown mode, even if the die temperature falls, until Bit 1 in the control register is cleared to 0. ...

Page 22

... X1A, X1B, M, and C registers, and the DAC data registers are updated by LDAC . The serial word (see is 24 bits long: 16 (AD5362 (AD5363) of these bits are data bits; six bits are address bits; and two bits are mode bits that determine what is done with the data. Two bits are reserved on the AD5363 ...

Page 23

... CHANNEL ADDRESSING AND SPECIAL MODES If the mode bits are not 00, the data-word D15 to D0 (AD5362) or D13 to D0 (AD5363) is written to the device. Address Bit A4 to Address Bit A0 determine which channels are written to, and the mode bits determine to which register (X1A, X1B ...

Page 24

... AD5362/AD5363 SPECIAL FUNCTION MODE If the mode bits are 00, the special function mode is selected, as shown in Table 15. Bit I21 to Bit I16 of the serial data-word select the special function, and the remaining bits are data required for execution of the special function, for example, the channel address for data readback ...

Page 25

... Bits Reserved Reserved DAC 3 Reserved Reserved DAC 7 Rev Page AD5362/AD5363 F8 F7 Register Read X1A register X1B register C register M register 0 1 Control register 1 0 OFS0 data register 1 1 OFS1 data register 0 0 Reserved 1 0 A/B Select Register 0 ...

Page 26

... The printed circuit boards on which the AD5362/AD5363 are mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5362/AD5363 are in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. ...

Page 27

... MAX 0.65 TYP 0.05 MAX 0.02 NOM COPLANARITY 0.50 BSC 0.08 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2 Figure 28. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ × Body, Very Thin Quad (CP-56-1) Dimensions shown in millimeters Rev Page AD5362/AD5363 12.20 12.00 SQ 11. 10.20 TOP VIEW 10.00 SQ (PINS DOWN) 9. 0.38 0.32 0.22 0.30 0.23 0.18 PIN 1 ...

Page 28

... AD5363BSTZ-REEL −40°C to +85°C 1 AD5363BCPZ −40°C to +85°C 1 AD5363BCPZ-REEL7 −40°C to +85°C 1 EVAL-AD5363EBZ RoHS Compliant Part. ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...

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