ADAU1701JSTZ Analog Devices Inc, ADAU1701JSTZ Datasheet
ADAU1701JSTZ
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ADAU1701JSTZ Summary of contents
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FEATURES 28-/56-bit, 50 MIPS digital audio processor Two ADCs: SNR of 100 dB, THD + N of −83 dB Four DACs: SNR of 104 dB, THD + N of −90 dB Complete standalone operation Self-boot from serial EEPROM Auxiliary ADC ...
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ADAU1701 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Analog Performance .................................................................... 3 Digital Input/Output.................................................................... 4 Power.............................................................................................. 4 Temperature Range ...................................................................... 4 PLL and Oscillator........................................................................ ...
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SPECIFICATIONS AVDD = 3.3 V, DVDD = 1.8 V, PVDD = 3.3 V, IOVDD = 3.3 V, ambient temperature 25° C, master clock input 12.288 MHz, unless otherwise noted. ANALOG PERFORMANCE Table 1. Parameter ADC INPUTS Number of Channels Resolution ...
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ADAU1701 DIGITAL INPUT/OUTPUT Table 2. Parameter Input Voltage, High ( Input Voltage, Low ( Input Leakage, High ( Input Leakage, Low ( Bidirectional Pin Pull-Up Current, Low MCLKI Input Leakage, High (I ...
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DIGITAL TIMING SPECIFICATIONS 1 Table 7. Digital Timing Parameter T MIN MASTER CLOCK 291 MP SERIAL PORT t 40 BIL t 40 BIH t 10 LIS t 10 LIH t ...
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ADAU1701 DIGITAL TIMING DIAGRAMS t BIH BCLK_IN t BIL t LIS LRCLK_IN t SIS SDATA_INX LEFT-JUSTIFIED MSB MODE t SIH SDATA_INX MODE SDATA_INX RIGHT-JUSTIFIED MODE 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 14-BIT CLOCKS (18-BIT DATA) ...
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CLS t CLATCH CCPH CCLK CDATA t CDS COUT t SCH SDA SCLK t MP MCLK RESET t CCPL t CDH Figure 4. SPI Port Timing SCR SCLH SCLL SCS SCF 2 ...
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ADAU1701 ABSOLUTE MAXIMUM RATINGS Table 8. Parameter Rating DVDD to GND 2.2 V AVDD to GND 4.0 V IOVDD to GND 4.0 V Digital Inputs DGND − 0.3 V, IOVDD + ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 10. Pin Function Descriptions Pin No. Mnemonic Type 1, 37, 42 AGND PWR 2 ADC1 A_IN 3 ADC_RES A_IN 4 ADC0 A_IN 5 RESET D_IN 6 SELFBOOT D_IN 7 ADDR0 D_IN 8 MP4 D_IO ...
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ADAU1701 Pin No. Mnemonic Type 14 MP7 D_IO 15 MP6 D_IO 16 MP10 D_IO 17 VDRIVE A_OUT 18 IOVDD PWR 19 MP11 D_IO 20 ADDR1/CDATA/WB D_IN 21 CLATCH/WP D_IO 22 SDA/COUT D_IO 23 SCL/CCLK D_IO 26 MP9 D_IO/A_IO 27 MP8 ...
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Pin No. Mnemonic Type 38 PLL_MODE0 D_IN 39 PLL_MODE1 D_IN 40 CM A_OUT 41 FILTD A_OUT 43 VOUT3 A_OUT 44 VOUT2 A_OUT 45 VOUT1 A_OUT 46 VOUT0 A_OUT 47 FILTA A_OUT 1 PWR = power/ground, A_IN = analog input, D_IN ...
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ADAU1701 TYPICAL PERFORMANCE CHARACTERISTICS 0.20 0.15 0.10 0.05 0 –0.05 –0.10 –0.15 –0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 FREQUENCY (kHz) Figure 8. ADC Pass-Band Filter Response –10 –20 –30 –40 –50 –60 –70 –80 –90 ...
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SYSTEM BLOCK DIAGRAM 18kΩ AUDIO ADC INPUT SIGNALS 18kΩ 18kΩ + 10µF MULTIPURPOSE PIN INTERFACES ADCs DACs 3.3V 3.3nF PLL SETTINGS 3 TO 25MHz 22pF 100Ω 22pF 3.3V 100nF 100nF 100nF 100nF 10µF 10µ IOVDD PVDD AVDD DVDD ...
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ADAU1701 OVERVIEW The core of the ADAU1701 is a 28-bit DSP (56-bit with double- precision processing) optimized for audio processing. The program and parameter RAMs can be loaded with a custom audio processing signal flow built by using SigmaStudio graphical ...
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INITIALIZATION This section details the procedure for properly setting up the ADAU1701. The following five-step sequence provides an overview of how to initialize the IC: 1. Apply power to ADAU1701. 2. Wait for PLL to lock. 3. Load SigmaDSP program ...
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ADAU1701 of these can be turned off by writing the appropriate bits in this register. The ADC power-down mode powers down both ADCs, and each DAC can be powered down individually. The current savings is about 15 ...
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VOLTAGE REGULATOR The digital voltage of the ADAU1701 must be set to 1.8 V. The chip includes an on-board voltage regulator that allows the device to be used in systems without an available 1.8 V supply but with an available ...
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ADAU1701 AUDIO ADCS The ADAU1701 has two Σ-Δ ADCs. The signal-to-noise ratio (SNR) of the ADCs is 100 dB and the THD + N is −83 dB. The stereo audio ADCs are current input; therefore, a voltage- to-current resistor is ...
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AUDIO DACS The ADAU1701 includes four Σ-Δ DACs. The SNR of the DAC is 104 dB and the THD + N is −90 dB. A full-scale output on the DACs is 0 rms p-p The DACs ...
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ADAU1701 CONTROL PORTS The ADAU1701 can operate in one of three control modes: • control • SPI control • Self-boot (no external controller) The ADAU1701 has both a 4-wire SPI control port and a 2 2-wire I ...
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I C PORT The ADAU1701 supports a 2-wire serial (I microprocessor bus driving multiple peripherals. Two pins, serial data (SDA) and serial clock (SCL), carry information between the ADAU1701 and the system mode, the ...
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ADAU1701 SCK SDA START BY MASTER CHIP ADDRESS BYTE SCK (CONTINUED) SDA (CONTINUED) SUBADDRESS BYTE 2 SCK SDA START BY MASTER FRAME 1 CHIP ADDRESS BYTE SCK (CONTINUED) SDA (CONTINUED) FRAME 3 SUBADDRESS BYTE 2 SCK (CONTINUED) ...
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I C Read and Write Operations Figure 22 shows the timing of a single-word write operation. Every ninth clock, the ADAU1701 issues an acknowledge by pulling SDA low. Figure 23 shows the timing of a burst mode write sequence. ...
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ADAU1701 SPI PORT 2 By default, the ADAU1701 mode, but can be put into SPI control mode by pulling CLATCH/WP low three times. The SPI port uses a 4-wire interface, consisting of CLATCH, CCLK, CDATA, and ...
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SELF-BOOT On power-up, the ADAU1701 can load a program and a set of parameters that have been saved in an external EEPROM. Combined with the auxiliary ADC and the multipurpose pins, this eliminates the need for a microcontroller in the ...
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ADAU1701 The writeback function writes data from the ADAU1701 interface registers to the second page of the self-boot EEPROM, Address 32 to Address 63. Starting at EEPROM Address 26 (so that the interface register data begins at Address 32), the ...
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SIGNAL PROCESSING The ADAU1701 is designed to provide all audio signal processing functions commonly used in stereo or multichannel playback systems. The signal processing flow is designed using the SigmaStudio software, which allows graphical entry and real- time control of ...
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ADAU1701 RAMS AND REGISTERS Table 21. RAM Map and Read/Write Modes Memory Size Parameter RAM 1024 × 32 Program RAM 1024 × Internal registers should be cleared first to avoid clicks/pops. ADDRESS MAPS Table 21 shows the RAM ...
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Table 22. Parameter RAM Read/Write Format (Single Address) Byte 0 Byte 1 chip_adr [6:0], W/R 000000, param_adr [9:8] Table 23. Parameter RAM Block Read/Write Format (Burst Mode) Byte 0 Byte 1 chip_adr [6:0], W/R 000000, param_adr [9:8] Table 24. Program ...
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ADAU1701 CONTROL REGISTER MAP 1 Table 32. Register Map No. Reg Reg of (Hex) (Dec) Bytes Name 0x0800 2048 4 Interface 0 [31:16] Interface 0 [15:0] 0x0801 2049 4 Interface 0 [31:16] Interface 0 [15:0] 0x0802 2050 4 Interface 0 ...
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No. of Reg Reg (Hex) (Dec) Bytes Name 0x081A 2074 2 Data Capture 0 0x081B 2075 2 Data Capture 1 0x081C 2076 2 DSP core control 0x081D 2077 1 Reserved 0x081E 2078 2 Serial output control 0x081F 2079 1 Serial ...
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ADAU1701 CONTROL REGISTER DETAILS 2048 TO 2055 (0X0800 TO 0X0807)—INTERFACE REGISTERS The interface registers are used in self-boot mode to save parameters that need to be written to the external EEPROM. The ADAU1701 then recalls these parameters from the EEPROM ...
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PIN SETTING REGISTER This register allows the user to set the GPIO pins through the control port. High or low settings can be directly written to or read from this register after setting the GPIO pin setting register ...
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ADAU1701 2057 TO 2060 (0x809 TO 0x80C)—AUXILIARY ADC DATA REGISTERS These registers hold the data generated by the 4-channel auxiliary ADC. The ADCs have eight bits of precision and can be extended to 12 bits if filtering is selected in ...
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TO 2068 (0x0810 TO 0x814)—SAFELOAD DATA REGISTERS Many applications require real-time microcontroller control of signal processing parameters, such as filter coefficients, mixer gains, multichannel virtualizing parameters, or dynamics processing curves. When controlling a biquad filter, for example, all of ...
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ADAU1701 2074 TO 2075 (0X081A TO 0X081B)—DATA CAPTURE REGISTERS The ADAU1701 data capture feature allows the data at any node in the signal processing flow to be sent to one of two readable registers. This feature is useful for monitoring ...
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CORE CONTROL REGISTER Table 46. D15 D14 D13 D12 D11 RSVD RSVD GD1 GD0 RSVD Table 47. DSP Core Control Register Bit Name Description GD [1:0] Sets debounce time of multipurpose pins that are set as GPIO inputs. ...
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ADAU1701 2078 (0x081E)—SERIAL OUTPUT CONTROL REGISTER Table 48. D15 D14 D13 D12 D11 D10 0 0 OLRP OBP M/S OBF1 Table 49. Bit Name Description OLRP When this bit is set to 0, the left-channel data is clocked when OUTPUT_LRCLK ...
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INPUT CONTROL REGISTER Table 50 Table 51. Bit Name Description ILP When this bit is set to 0, the left-channel data on the SDATA_INx pins is clocked when INPUT_LRCLK is low and ...
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ADAU1701 2080 TO 2081 (0x0820 TO 0x0821)—MULTIPURPOSE PIN CONFIGURATION REGISTERS Each multipurpose pin can be set to different functions from these registers (2080 to 2081). The two 3-byte registers are broken up into 12 4-bit (nibble) sections that each control ...
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ADC AND POWER CONTROL Table 55. D15 D14 D13 D12 D11 RSVD RSVD RSVD RSVD RSVD Table 56. Bit Name Description FIL [1:0] Auxiliary ADC filtering FIL [1: AAPD ADC power-down (both ADCs) VBPD ...
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ADAU1701 2087 (0x0827)—DAC SETUP To properly initialize the DACs, Bits DS [1:0] in this register should be set to 01. Table 61. D15 D14 D13 D12 D11 RSVD RSVD RSVD RSVD RSVD Table 62. Bit Name Description DS [1:0] DAC ...
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MULTIPURPOSE PINS The ADAU1701 has 12 multipurpose (MP) pins that can be individually programmed to be used as serial data inputs, serial data outputs, digital control inputs/outputs to and from the SigmaDSP core, or inputs to the 4-channel auxiliary ADC. ...
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ADAU1701 The input control register allows control of clock polarity and data input modes. The valid data formats are I right-justified (24-/20-/18-/16-bit), and 8-channel TDM. In all modes except for the right-justified modes, the serial port accepts an arbitrary number ...
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LEFT CHANNEL LRCLK BCLK SDATA MSB LRCLK LEFT CHANNEL BCLK MSB SDATA Figure 32. Left-Justified Mode—16 Bits to 24 Bits per Channel LEFT CHANNEL LRCLK BCLK SDATA MSB Figure 33. Right-Justified Mode—16 Bits to 24 Bits per Channel LRCLK BCLK ...
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ADAU1701 LAYOUT RECOMMENDATIONS PARTS PLACEMENT The ADC input voltage-to-current resistors and the ADC current set resistor should be placed as close as possible to the 2, 3, and 4 input pins. All 100 nF bypass capacitors, which are recommended for ...
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TYPICAL APPLICATION SCHEMATICS SELF-BOOT MODE Figure 36. Self-Boot Mode Schematic Rev Page ADAU1701 ...
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ADAU1701 CONTROL 2 Figure 37 Control Schematic Rev Page ...
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SPI CONTROL Figure 38. SPI Control Schematic Rev Page ADAU1701 ...
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... ADAU1701 OUTLINE DIMENSIONS 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range 1 ADAU1701JSTZ 0°C to 70°C 1 ADAU1701JSTZ-RL 0°C to 70°C EVAL-ADAU1701EB Pb-free part. 9.20 9.00 SQ 0.75 1.60 8.80 0.60 MAX 0. PIN 1 TOP VIEW 0.20 (PINS DOWN) 0 ...
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NOTES Rev Page ADAU1701 ...
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ADAU1701 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06412-0-10/06(0) Rev Page ...