AD5755-1 Analog Devices, AD5755-1 Datasheet - Page 38

• Manufacturer Part Number: AD5755-1
• Description: Quad Channel, 16-Bit, Serial Input, 4-20mA & Voltage Output DAC, Dynamic Power Control, HART Connectivity
• Manufacturer: Analog Devices

Specifications of AD5755-1

• Resolution (bits): 16bit
• Dac Update Rate: 91kSPS
• Dac Settling Time: 11µs
• Max Pos Supply (v): +33V
• Single-supply: No
• Dac Type: I or V Out
• Dac Input Format: SPI

AD5755-1
Slew Rate Control Register
This register is used to program the slew rate control for the
selected DAC channel. This feature is available on both the
current and voltage outputs. The slew rate control is enabled/
disabled and programmed on a per channel basis. See Table 26
and the Digital Slew Rate Control section for more information.
READBACK OPERATION
Readback mode is invoked by setting the R/ W bit = 1 in the
serial input register write. See Table 27 for the bits associated
with a readback operation. The DUT_AD1 and DUT_AD0 bits,
in association with Bits RD[4:0], select the register to be read.
The remaining data bits in the write sequence are don’t cares.
During the next SPI transfer (see Figure 4), the data appearing
on the SDO output contains the data from the previously
addressed register. This second SPI transfer should either be a
Table 26. Programming the Slew Rate Control Register
D15
0
1
Table 27. Input Shift Register Contents for a Read Operation
D23
R/W
1
Table 28. Read Address Decoding
RD4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
X = don’t care.
X = don’t care.
D22
DUT_AD1
RD3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
D14
0
D21
DUT_AD0
D13
0
RD2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
D12
SREN
D20
RD4
RD1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
Rev. B | Page 38 of 52
D11 to D7
X
D19
RD3
RD0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
request to read yet another register on a third data transfer or a
no operation command. The no operation command for DUT
Address 00 is 0x1CE000, for other DUT addresses, Bits D22 and
D21 are set accordingly.
Readback Example
To read back the gain register of Device 1, Channel A on the
AD5755-1, implement the following sequence:
1.
2.
D18
RD2
Function
Read DAC A data register
Read DAC B data register
Read DAC C data register
Read DAC D data register
Read DAC A control register
Read DAC B control register
Read DAC C control register
Read DAC D control register
Read DAC A gain register
Read DAC B gain register
Read DAC C gain register
Read DAC D gain register
Read DACA offset register
Read DAC B offset register
Read DAC C offset register
Read DAC D offset register
Clear DAC A code register
Clear DAC B code register
Clear DAC C code register
Clear DAC D code register
DAC A slew rate control register
DAC B slew rate control register
DAC C slew rate control register
DAC D slew rate control register
Read status register
Read main control register
Read dc-to-dc control register
Write 0xA80000 to the AD5755-1 input register. This
configures the AD5755-1 Device Address 1 for read mode
with the gain register of Channel A selected. All the data
bits, D15 to D0, are don’t cares.
Follow with another read command or a no operation
command (0x3CE000). During this command, the data
from the Channel A gain register is clocked out on the
SDO line.
D17
RD1
D6 to D3
SR_CLOCK
D16
RD0
D15 to D0
X
D2 to D0
SR_STEP
1
Data Sheet