AD9861 Analog Devices, AD9861 Datasheet - Page 39

• Manufacturer Part Number: AD9861
• Manufacturer: Analog Devices

Specifications of AD9861

• Resolution (bits): 10bit
• # Chan: 2
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

Register Bit
Register 13: I/O Configuration
Register 14: I/O Configuration
Register 15: Clock
Register 16: Clock
Bit 4: TxPGA Fast Update (Mode)
Bit 7: Tx Twos Complement
Bit 6: Rx Twos Complement
Bit 5: Tx Inverse Sample
Bits 1,0: Interpolation Control
Bit 5: Dig Loop On
Bit 4: SPI_FDnHD
Bit 3: SpiTxnRx
Bit 2: SpiB10n20
Bit 1: SPI IO Control
Bit 0: SpiClone
Bit 7: PLL_Bypass
Bits 5: ADC Clock Div
Bit 4: Alt Timing Mode
Bit 3: PLL Div5
Bits 2–0: PLL Multiplier
Bit 5: PLL to IFACE2
Bit 2: PLL Slow
Description
The TxPGA fast bit controls the update speed of the TxPGA. When fast update mode is enabled, the
TxPGA provides fast gain settling within a few clock cycles, which may introduce spurious signals at
the output of the Tx path. The default setting for this bit is low, and the TxPGA gives a smooth
transition between gain settings. Fast mode is enabled when this bit is set high.
The default data format for Tx data is straight binary. Set this bit high when providing twos
complement Tx data.
The default data format for Rx data is straight binary. Set this bit high when providing twos
complement Rx data.
By default, the transmit data is sampled on the rising edge of the CLKOUT. Setting this bit high
changes this, and the transmit data is sampled on the falling edge.
These register bits control the interpolation rate of the transmit path. The default settings are both
bits low, indicating that both interpolation filters are bypassed. The MSB and LSB are Address Bits 1
and 0, respectively. Setting binary 01 provides an interpolation rate of 2×; binary 10 provides an
interpolation rate of 4×.
When enabled, this bit enables a digital loop back mode. The digital loop-back mode provides a
means of testing digital interfaces and functionality at the system level. In digital loop-back mode,
the full-duplex interface must be enabled. (Refer to the Flexible I/O Interface Options section.) The
device accepts digital input from the bus according to the FD mode timing and uses the Tx digital
path (with enabled interpolation and other digital settings); the processed data is then output from
the Rx path bus.
Control bit to configure full-duplex (high) or half-duplex (low) interface mode. This register, in
combination with the SpiB10n20 register, configures the interface mode of FD, HD10, or HD20. The
register setting is ignored for clone mode operation. By default, this register is set high, and the
device is in FD mode.
Control bit used for toggling between transmit or receive mode for the half-duplex clock modes.
High represents Tx and low represents Rx.
Control bit for 10-bit or 20-bit modes. High represents 10-bit mode and Low represents 20-bit mode.
Use in conjunction with SpiTxnRx [Register14, Bit 3] to override external TxnRx pin operation.
Set high when in clone mode (see the Flexible I/O Interface Options section for definition of clone
mode). Clk_mode should also be set to binary 111, i.e., [Register 01[7:5] = 111.
Setting this bit high bypasses the PLL. When bypassed, the PLL remains active.
By default, the ADCs are driven directly from CLKIN in normal timing operation or from the PLL
output clock in the alternative timing operation. This bit is used to divide the source of the ADC
clock prior to the ADCs. The default setting is low and performs no division. Setting this bit high
divides the clock by 2.
The timing table in the data sheet describes two timing modes: the normal timing operation mode
and the alternative timing operation mode. The default configuration is normal timing mode and
the CLKIN drives the Rx path. In alternative timing mode, the PLL output is used to drive the Rx
path. The alternative operation mode is configured by setting this bit high.
The output of the PLL can be divided by 5 by setting this bit high. By default, the PLL directly drives
the Tx digital path with no division of its output.
These bits control the PLL multiplication factor. A default setting is binary 000, which configures the
PLL to 1× multiplication factor. This register, in combination with the PLL Div5 register, sets the PLL
output frequency. The programmable multiplication factors are
Setting this bit high switches the IFACE2 output signal to the PLL output clock. It is valid only if
Register 0x01, Bit 2 is enabled or if full-duplex mode is configured.
Changes the PLL loop bandwidth and changes the profile of the phase noise generated from the
PLL clock.
000
001
010
011
100
101 – 111
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1×
2×
4×
8×
16×
not used
AD9861