AD9861 Analog Devices, AD9861 Datasheet - Page 5
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AD9861
Manufacturer Part Number
AD9861
Description
Manufacturer
Analog Devices
Datasheet
1.AD9861.pdf
(52 pages)
Specifications of AD9861
Resolution (bits)
10bit
# Chan
2
Sample Rate
80MSPS
Interface
Par
Analog Input Type
Diff-Uni
Ain Range
2 V p-p
Adc Architecture
Pipelined
Pkg Type
CSP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD9861BCP
Manufacturer:
ADI
Quantity:
296
Company:
Part Number:
AD9861BCP-50
Manufacturer:
AD
Quantity:
1 000
Part Number:
AD9861BCP-50
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
AD9861BCP-80
Manufacturer:
ADI
Quantity:
300
Part Number:
AD9861BCPZ-50
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD9861BCPZ-80
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
AD9861BCPZRL-50
Manufacturer:
AD
Quantity:
13 821
POWER SPECIFICATIONS
Table 3. AD9861-50 and AD9861-80
Analog and digital supplies = 3.3 V; F
Parameter
POWER SUPPLY RANGE
ANALOG SUPPLY CURRENTS
DIGITAL SUPPLY CURRENTS
DIGITAL SPECIFICATIONS
Table 4. AD9861-50 and AD9861-80
Parameter
LOGIC LEVELS
DIGITAL PIN
Analog Supply Voltage (AVDD)
Digital Supply Voltage (DVDD)
Driver Supply Voltage (DRVDD)
TxPath (20 mA Full-Scale Outputs)
TxPath (2 mA Full-Scale Outputs)
Rx Path (-80, at 80 MSPS)
RxPath (-80, at 40 MSPS, Low Power Mode)
RxPath (-80, at 20 MSPS, Ultralow Power Mode)
Rx Path (-50, at 50 MSPS)
RxPath (-50, at 50 MSPS, Low Power Mode)
RxPath (-50, at 16 MSPS, Ultralow Power Mode)
TxPath, Power-Down Mode
RxPath, Power-Down Mode
PLL
TxPath, 1× Interpolation,
TxPath, 2× Interpolation,
TxPath, 4× Interpolation,
RxPath Digital, Half-Duplex 24 Mode
Input Logic High Voltage, V
Input Logic Low Voltage, V
Output Logic High Voltage, V
Output Logic Low Voltage, V
Input Leakage Current
Input Capacitance
Minimum RESET Low Pulse Width
Digital Output Rise/Fall Time
50 MSPS DAC Update for Both DACs,
Half-Duplex 24 Mode
100 MSPS DAC Update for Both DACs,
Half-Duplex 24 Mode
200 MSPS DAC Update for Both DACs,
Half-Duplex 24 Mode
IL
IH
OL
OH
(1 mA Load)
(1 mA Load)
CLKIN
= 50 MHz; PLL 4× setting; normal timing mode
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Rev. 0 | Page 5 of 52
Test Level
IV
IV
IV
IV
IV
IV
IV
IV
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level
IV
IV
IV
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Min
DRVDD – 0.7
DRVDD – 0.6
5
2.8
3
Min
2.7
2.7
2.7
Typ
Max
0.4
0.4
12
4
Typ
70
20
165
82
35
103
69
28
2
5
12
20
50
80
15
Unit
V
V
V
V
µA
pF
Input Clock Cycles
ns
Max
3.6
3.6
3.6
AD9861
V
mA
mA
mA
mA
mA
Unit
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA