AD7666 Analog Devices, AD7666 Datasheet - Page 7

• Manufacturer Part Number: AD7666
• Manufacturer: Analog Devices

Specifications of AD7666

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 500kSPS
• Interface: Par,Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p,2.5V p-p,Uni (Vref),Uni 2.5V
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

ABSOLUTE MAXIMUM RATINGS
Table 5. AD7666 Stress Ratings
Parameter
IN
Ground Voltage Differences
Supply Voltages
Digital Inputs
PDREF, PDBUF
Internal Power Dissipation
Internal Power Dissipation
Junction Temperature
Storage Temperature Range
Lead Temperature Range
1
2
3
4
5
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although this product features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those listed
in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
See Analog Input section.
See the Voltage Reference Input section.
Specification is for the device in free air:
48-Lead LQFP; θ
Specification is for the device in free air:
48-Lead LFCSP; θ
2
REFGND to AGND
AGND, DGND, OGND
AVDD, DVDD, OVDD
AVDD to DVDD, AVDD to OVDD
DVDD to OVDD
(Soldering 10 sec)
, TEMP
2
, REF, REFBUFIN, INGND,
3
JA
JA
= 91°C/W, θ
= 26°C/W.
JC
4
5
= 30°C/W
1
Rating
AVDD + 0.3 V to
±0.3 V
–0.3 V to +7 V
±7 V
–0.3 V to +7 V
–0.3 V to DVDD + 0.3 V
±20 mA
700 mW
2.5 W
150°C
–65°C to +150°C
300°C
AGND – 0.3 V
Rev. 0 | Page 7 of 28
t
* IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND
TO OUTPUT
0.8V
DELAY
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
C
L
Figure 2. Load Circuit for Digital Interface Timing,
OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM.
Figure 3. Voltage Reference Levels for Timing
PIN
SDOUT, SYNC, SCLK Outputs C
60pF *
2V
0.8V
C
L
500µA
1.6mA
I
I
OH
OL
2V
L
= 10 pF
t
DELAY
2V
0.8V
1.4V
AD7666