AD7666 Analog Devices, AD7666 Datasheet - Page 26

no-image

AD7666

Manufacturer Part Number
AD7666
Description
Manufacturer
Analog Devices
Datasheet

Specifications of AD7666

Resolution (bits)
16bit
# Chan
1
Sample Rate
500kSPS
Interface
Par,Ser,SPI
Analog Input Type
Diff-Uni
Ain Range
(Vref) p-p,2.5V p-p,Uni (Vref),Uni 2.5V
Adc Architecture
SAR
Pkg Type
CSP,QFP

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD7666AST
Manufacturer:
ADI
Quantity:
300
Part Number:
AD7666AST
Manufacturer:
AD
Quantity:
8 000
Part Number:
AD7666ASTZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
AD7666ASTZRL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
AD7666
MICROPROCESSOR INTERFACING
The AD7666 is ideally suited for traditional dc measurement
applications supporting a microprocessor, and for ac signal
processing applications interfacing to a digital signal processor.
The AD7666 is designed to interface either with a parallel 8-bit
or 16-bit wide interface, or with a general-purpose serial port or
I/O ports on a microcontroller. A variety of external buffers can
be used with the AD7666 to prevent digital noise from coupling
into the ADC. The following section discusses the use of an
AD7666 with an ADSP-219x SPI equipped DSP.
SPI Interface (ADSP-219x)
Figure 44 shows an interface diagram between the AD7666 and
the SPI equipped ADSP-219x. To accommodate the slower
speed of the DSP, the AD7666 acts as a slave device and data
must be read after conversion. This mode also allows the daisy-
chain feature. The convert command can be initiated in
response to an internal timer interrupt. The reading process can
be initiated in response to the end-of-conversion signal (BUSY
Rev. 0 | Page 26 of 28
going LOW) using an interrupt line of the DSP. The serial inter-
face (SPI) on the ADSP-219x is configured for master mode—
(MSTR) = 1, Clock Polarity bit (CPOL) = 0, Clock Phase bit
(CPHA) = 1, and SPI Interrupt Enable (TIMOD) = 00—by
writing to the SPI control register (SPICLTx). To meet all timing
requirements, the SPI clock should be limited to 17 Mbps,
which allows it to read an ADC result in less than 1 µs. When a
higher sampling rate is desired, use of one of the parallel
interface modes is recommended.
DVDD
SER/PAR
EXT/INT
RD
INVSCLK
Figure 44. Interfacing the AD7666 to an SPI Interface
AD7666*
* ADDITIONAL PINS OMITTED FOR CLARITY
SDOUT
CNVST
BUSY
SCLK
CS
SPIxSEL (PFx)
PFx
MISOx
SCKx
PFx or TFSx
ADSP-219x*

Related parts for AD7666