AD7687 Analog Devices, AD7687 Datasheet - Page 18

• Manufacturer Part Number: AD7687
• Manufacturer: Analog Devices

Specifications of AD7687

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 250kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: CSP,SOP

AD7687
CS MODE 3-WIRE, NO BUSY INDICATOR
This mode is usually used when a single AD7687 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 35 and the corresponding timing is given in
Figure 36.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it continues to
completion irrespective of the state of CNV. For instance, it
could be useful to bring CNV low to select other SPI devices,
such as analog multiplexers, but CNV must be returned high
before the minimum conversion time and held high until the
maximum conversion time to avoid the generation of the BUSY
signal indicator. When the conversion is complete, the AD7687
enters the acquisition phase and powers down. When CNV
goes low, the MSB is output onto SDO. The remaining data bits
are then clocked by subsequent SCK falling edges. The data is
valid on both SCK edges. Although the rising edge can be used
ACQUISITION
SDI = 1
CNV
SCK
SDO
t
CNVH
CONVERSION
t
CONV
Figure 36. CS Mode 3-Wire, No BUSY Indicator Serial Interface Timing (SDI High)
t
EN
D15
1
t
HSDO
Rev. B | Page 18 of 28
D14
2
t
CYC
ACQUISITION
to capture the data, a digital host using the SCK falling edge
allows a faster reading rate provided it has an acceptable hold
time. After the 16th SCK falling edge or when CNV goes high,
whichever is earlier, SDO returns to high impedance.
D13
t
3
ACQ
VIO
t
DSDO
SDI
t
SCKL
t
AD7687
SCKH
Figure 35. CS Mode 3-Wire, No BUSY Indicator
14
CNV
SCK
Connection Diagram (SDI High)
t
SCK
15
SDO
D1
16
D0
CLK
CONVERT
DATA IN
t
DIGITAL HOST
DIS
Data Sheet