AD7686 Analog Devices, AD7686 Datasheet
AD7686
Specifications of AD7686
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AD7686 Summary of contents
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... The part also contains a low noise, wide bandwidth, short aperture delay track-and-hold circuit. On the CNV rising edge, the AD7686 samples an analog input IN+ between REF with respect to a ground sense IN−. The reference voltage, REF, is applied externally and can be set up to the supply voltage. ...
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... AD7686 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications....................................................................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configurations and Function Descriptions ........................... 7 Terminology ...................................................................................... 8 Typical Performance Characteristics ............................................. 9 Theory of Operation ...................................................................... 12 Circuit Information.................................................................... 12 Converter Operation.................................................................. 12 Typical Connection Diagram ................................................... 13 Analog Input ............................................................................... 14 REVISION HISTORY 3/07— ...
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... REF = 2.5 V 87.5 REF −106 −106 = REF = 5 V, −60 dB input 32 REF −110 Rev Page AD7686 C Grade Max Min Typ Max REF REF VDD + 0.1 −0.1 VDD + 0.1 +0.1 −0.1 +0 See the Analog Input section 16 − ...
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... AD7686 VDD = 4 5.5 V, VIO = 2 VDD, V Table 3. Parameter Conditions REFERENCE Voltage Range Load Current 500 kSPS, REF = 5 V SAMPLING DYNAMICS −3 dB Input Bandwidth Aperture Delay VDD = 5 V DIGITAL INPUTS Logic Levels DIGITAL OUTPUTS Data Format Pipeline Delay ...
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... TO SDO C L 50pF 500µ Figure 3. Load Circuit for Digital Interface Timing 30% VIO t DELAY 1. VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V. 2 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V. Rev Page AD7686 Symbol Min Typ Max t 0.5 1.6 CONV t 400 ACQ t 2 CYC t 10 ...
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... AD7686 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating Analog Inputs 1 1 IN+ , IN− GND − 0 VDD + 0 ±130 mA REF GND − 0 VDD + 0.3 V Supply Voltages VDD, VIO to GND −0 VDD to VIO ±7 V Digital Inputs to GND −0 VIO + 0.3 V Digital Outputs to GND − ...
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... AI = analog input digital input digital output, and P = power. VIO SDI SCK SDO CNV Rev Page REF 1 10 VIO VDD 2 9 SDI AD7686 IN SCK TOP VIEW IN– SDO (Not to Scale) GND 5 6 CNV Figure 6. 10-Lead QFN (LFCSP) Pin Configuration AD7686 . REF ...
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... AD7686 TERMINOLOGY Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition ...
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... CODE IN HEX Figure 11. Histogram Input at the Code Transition 95 94 THD 93 SNR –10 –8 –6 –4 INPUT LEVEL (dB) Figure 12. SNR and THD vs. Input Level AD7686 49152 65535 VDD = REF = 802A 802B –105 –108 –111 –114 –117 –120 –2 0 ...
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... AD7686 100 2.3 2.7 3.1 3.5 3.9 4.3 REFERENCE VOLTAGE (V) Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage 100 –55 –35 – TEMPERATURE (°C) Figure 14. SNR vs. Temperature 100 95 VREF = 5V, –10dB 90 VREF = 5V, –1dB 100 FREQUENCY (kHz) Figure 15. SINAD vs. Frequency 17.0 16.0 SNR SINAD 15 ...
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... Figure 22. Offset and Gain Error vs. Temperature 105 125 0 Figure 23 100kSPS S 85 105 125 Rev Page AD7686 OFFSET ERROR GAIN ERROR –35 – 105 TEMPERATURE (°C) VDD = 5V, 85°C VDD = 5V, 25° 100 SDO CAPACITIVE LOAD (pF) Delay vs ...
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... The AD7686 is specified from 4 5.5 V and can be interfaced to any of the 1 digital logic family housed in a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that combines space savings and allows flexible configurations ...
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... Transfer Functions The ideal transfer characteristic for the AD7686 is shown in Figure 25 and Table 7. 111...111 111...110 111...101 000...010 000...001 000...000 –FSR –FSR + 1 LSB –FSR + 0.5 LSB +FSR – 1.5 LSB ANALOG INPUT Figure 25. ADC Ideal Transfer Function ≥7V ≥ ...
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... AD7686 ANALOG INPUT Figure 27 shows an equivalent circuit of the input structure of the AD7686. The two diodes, D1 and D2, provide ESD protection for the analog inputs IN+ and IN−. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 V because this causes these diodes to begin to forward-bias and start conducting current ...
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... REF and GND pins. POWER SUPPLY The AD7686 is specified at 4 5.5 V. The device uses two power supply pins: a core supply VDD and a digital input/ output interface supply VIO. VIO allows direct interface with any logic between 1.8 V and VDD. To reduce the supplies needed, the VIO and VDD can be tied together ...
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... DIGITAL INTERFACE Though the AD7686 has a reduced number of pins, it offers flexibility in its serial interface modes. The AD7686, when in CS mode, is compatible with SPI, QSPI, digital hosts, and DSPs, such as Blackfin® ADSP-BF53x or ADSP-219x. This interface can use either 3-wire or 4-wire. A 3-wire interface using the CNV, SCK, and SDO signals minimizes wiring connections useful, for instance, in isolated applications ...
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... CS MODE 3-WIRE, NO BUSY INDICATOR This mode is most often used when a single AD7686 is connected to an SPI-compatible digital host. The connection diagram is shown in Figure 33, and the corresponding timing is provided in Figure 34. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance ...
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... AD7686 CS MODE 3-WIRE WITH BUSY INDICATOR This mode is generally used when a single AD7686 is connected to an SPI-compatible digital host having an interrupt input. The connection diagram is shown in Figure 35, and the correspond- ing timing is provided in Figure 36. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance ...
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... Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the 16th SCK falling edge or when SDI goes high, whichever occurs first, SDO returns to high impedance and another AD7686 can be read. CNV CNV ...
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... AD7686 CS MODE 4-WIRE WITH BUSY INDICATOR This mode is usually used when a single AD7686 is connected to an SPI-compatible digital host, which has an interrupt input, and when it is desired to keep CNV, which is used to sample the analog input, independent of the signal used to select the data reading ...
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... AD7686s in the chain, provided the digital host has an acceptable hold time. The maximum conversion rate can be reduced due to the total readback time. For instance, with digital host setup time and 3 V interface four AD7686s running at a conversion rate of 360 kSPS can be daisy-chained on a 3-wire port. ...
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... AD7686s in the chain, provided the digital host has an acceptable hold time. For instance, with digital host setup time and 3 V interface four AD7686s running at a conversion rate of 360 kSPS can be daisy chained to a single 3-wire port. CNV ...
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... The pinout of the AD7686, with all its analog signals on the left side and all its digital signals on the right side, eases this task. Avoid running digital lines under the device because doing so couples noise onto the die, unless a ground plane under the AD7686 is used as a shield ...
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... ADuM1402C digital isolator, provides a compact and high performance solution. Multiple AD7686 devices are daisy-chained to reduce the number of signals to isolate. Note that the SCKOUT, which is a readback of the AD7686 clock, has a very short skew with the DATA signal. 5V REF 4kΩ 1kΩ ±10V INPUT ...
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... Figure 49. 10-Lead Lead Frame Chip Scale Package [QFN (LFCSP_WD × Body, Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters Rev Page 0.80 8° 0.60 0° 0.40 PIN 1 INDICATOR 1 2.48 2.38 2.23 5 PADDLE CONNECTED TO GND. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES AD7686 ...
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... LSB max 1 AD7686BRMZ ±3 LSB max 1 AD7686BRMZRL7 ±3 LSB max 1 AD7686CCPZRL ±2 LSB max 1 AD7686CCPZRL7 ±2 LSB max AD7686CRM ±2 LSB max AD7686CRMRL7 ±2 LSB max AD7686CRMZ 1 ±2 LSB max 1 AD7686CRMZRL7 ±2 LSB max 2 EVAL-AD7686CB 1, 2 EVAL-AD7686CBZ EVAL-CONTROL BRD2 3 3 EVAL-CONTROL BRD3 RoHS Compliant Part, # denotes RoHS Compliant product may be top or bottom marked ...
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... NOTES Rev Page AD7686 ...
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... AD7686 NOTES ©2005–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02969-0-3/07(B) Rev Page ...