AD7277 Analog Devices, AD7277 Datasheet - Page 19

• Manufacturer Part Number: AD7277
• Description: 3 MSPS,10-Bit ADC in 6-Lead TSOT
• Manufacturer: Analog Devices

Specifications of AD7277

• Resolution (bits): 10bit
• # Chan: 1
• Sample Rate: 3MSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni Vdd
• Adc Architecture: SAR
• Pkg Type: SOP,SOT

To exit this mode of operation and power up the AD7276/
AD7277/AD7278, users should perform a dummy conversion.
On the falling edge of
continues to power up as long as
falling edge of the 10
once 16 SCLKs elapse; valid data results from the next conversion,
as shown in
edge of SCLK, the AD7276/AD7277/AD7278 go into full power-
down mode. Therefore, although the device can begin to power
up on the falling edge of CS , it powers down on the rising edge
of CS as long as this occurs before the 10
If the AD7276/AD7277/AD7278 are already in partial power-
down mode and
of SCLK, the device enters full power-down mode. For more
information on the power-up times associated with partial
power-down mode in various configurations, see the
Times
Full Power-Down Mode
This mode is intended for use in applications where throughput
rates slower than those in the partial power-down mode are
required because power-up from a full power-down takes
substantially longer than that from a partial power-down. This
mode is suited to applications where a series of conversions
performed at a relatively high throughput rate are followed by a
long period of inactivity and thus, power down.
When the AD7276/AD7277/AD7278 are in full power-down
mode, all analog circuitry is powered down. To enter full power-
down mode, put the device into partial power-down mode by
bringing CS high between the second and 10
SCLK. In the next conversion cycle, interrupt the conversion
process in the same way as shown in
high before the 10
in this window of SCLKs, the part powers down completely.
Note that it is not necessary to complete the 16 SCLKs once CS is
brought high to enter either of the power-down modes. Glitch
protection is not available when entering full power-down mode.
To exit full power-down mode and to power up the AD7276/
AD7277/AD7278, users should perform a dummy conversion,
similar to when powering up from partial power-down mode.
On the falling edge of CS , the device begins to power up and
continues to power up as long as CS is held low until after the
falling edge of the 10
elapse before a conversion can be initiated, as shown in
See the
associated with the AD7276/AD7277/AD7278.
section.
Power-Up Times
Figure 26
CS
th
SCLK falling edge. Once CS is brought high
is brought high before the 10
th
th
. If
CS
SCLK. The device is fully powered up
SCLK. The required power-up time must
CS is brought high before the 10
, the device begins to power up and
section for the power-up times
CS
is held low until after the
Figure 27
th
SCLK falling edge.
th
falling edges of
by bringing
th
falling edge
Figure 28
Power-Up
th
falling
CS
Rev. C | Page 19 of 28
.
Power-Up Times
The AD7276/AD7277/AD7278 have two power-down modes,
partial power-down and full power-down, which are described
in detail in the Modes of Operation section. This section deals
with the power-up time required when coming out of either of
these modes.
To power up from partial power-down mode, one cycle is
required. Therefore, with an SCLK frequency of up to 48 MHz,
one dummy cycle is sufficient to allow the device to power up
from partial power-down mode. Once the dummy cycle is
complete, the ADC is fully powered up and the input signal is
acquired properly. The quiet time, t
from the point where the bus goes back into three-state after the
dummy conversion to the next falling edge of
To power up from full power-down, approximately 1 μs should
be allowed from the falling edge of
t
Note that during power-up from partial power-down mode, the
track-and-hold, which is in hold mode while the part is
powered down, returns to track mode after the first SCLK edge,
following the falling edge of
Figure 26
When power supplies are first applied to the AD7276/AD7277/
AD7278, the ADC can power up in either of the power-down
modes or in normal mode. Because of this, it is best to allow a
dummy cycle to elapse to ensure that the part is fully powered
up before attempting a valid conversion. Likewise, if the part is
to be kept in partial power-down mode immediately after the
supplies are applied, then two dummy cycles must be initiated.
The first dummy cycle must hold
SCLK falling edge; in the second cycle,
between the second and 10
Alternatively, if the part is to be placed into full power-down
mode when the supplies are applied, three dummy cycles must
be initiated. The first dummy cycle must hold CS low until after
the 10
place the part into full power-down mode (see
the
POWER UP
Modes of Operation
th
SCLK falling edge; the second and third dummy cycles
.
.
section.
AD7276/AD7277/AD7278
th
CS
SCLK falling edges (see
. This is shown as Point A in
CS
CS
QUIET
low until after the 10
, shown in
CS
, must still be allowed
must be brought high
CS
Figure 27
.
Figure 28
Figure 25
). See
th
as
).