AD7277 Analog Devices, AD7277 Datasheet
AD7277
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AD7277 Summary of contents
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... AD7476A pin-compatible GENERAL DESCRIPTION The AD7276/AD7277/AD7278 are 12-/10-/8-bit, high speed, low power, successive approximation analog-to-digital converters (ADCs), respectively. The parts operate from a single 2. 3.6 V power supply and feature throughput rates MSPS. The parts contain a low noise, wide bandwidth track- and-hold amplifier that can handle input frequencies in excess of 55 MHz ...
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... Features .............................................................................................. 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 AD7276 Specifications................................................................. 3 AD7277 Specifications................................................................. 5 AD7278 Specifications................................................................. 7 Timing Specifications—AD7276/AD7277/AD7278 ............... 8 Timing Examples........................................................................ 10 Absolute Maximum Ratings.......................................................... 11 ESD Caution................................................................................ 11 Pin Configurations and Function Descriptions ......................... 12 Typical Performance Characteristics ........................................... 13 Terminology .................................................................................... 15 REVISION HISTORY 5/11—Rev Rev. C Changes to Figure 21 ...
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... V − 0.2 V min DD DD 0.2 0.2 V max ±2.5 ±2.5 μA max 4.5 4.5 pF typ Straight (natural) binary Rev Page AD7276/AD7277/AD7278 MHz MSPS SCLK SAMPLE A Test Conditions/Comments MHz sine wave, B Grade 100 kHz sine wave, Y Grade MHz 0.97 MHz MHz 0.97 MHz @ ...
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... AD7276/AD7277/AD7278 Parameter CONVERSION RATE Conversion Time 4 Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS Normal Mode (Static) Normal Mode (Operational) Partial Power-Down Mode (Static) Full Power-Down Mode (Static) 6 Power Dissipation Normal Mode (Operational) Partial Power-Down Full Power-Down 1 Y Grade specifications are guaranteed by characterization. ...
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... AD7277 SPECIFICATIONS MHz SCLK SAMPLE Table 3. Parameter DYNAMIC PERFORMANCE 3 Signal-to-Noise + Distortion (SINAD) 3 Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR) Intermodulation Distortion (IMD) 3 Second-Order Terms Third-Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth DC ACCURACY ...
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... AD7276/AD7277/AD7278 Parameter POWER REQUIREMENTS Normal Mode (Static) Normal Mode (Operational) Partial Power-Down Mode (Static) Full Power-Down Mode (Static) 5 Power Dissipation Normal Mode (Operational) Partial Power-Down Full Power-Down 1 Temperature range from −40°C to +125°C. 2 Typical specifications are tested with and at 25° ...
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... V − 0 0.2 0.2 ±2.5 ±2.5 4.5 4.5 Straight (natural) binary 208 208 Rev Page AD7276/AD7277/AD7278 Unit Test Conditions/Comments MHz sine wave IN dB min dB max dB typ dB typ dB typ MHz 0.97 MHz dB typ MHz 0.97 MHz MHz typ @ 3 dB MHz typ @ 0.1 dB Bits ...
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... Temperature range from −40°C to +125°C. 2 Typical specifications are tested with and at 25° See the Terminology section. 4 Guaranteed by characterization. 5 See the Power vs. Throughput Rate section. TIMING SPECIFICATIONS—AD7276/AD7277/AD7278 MIN MAX Table 5. Parameter ...
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... SCLK SDATA Figure 2. Access Time After SCLK Falling Edge t 7 SCLK V IH SDATA V IL Figure 3. Hold Time After SCLK Falling Edge SCLK V IH SDATA V IL Figure 4. SCLK Falling Edge SDATA Three-State Rev Page AD7276/AD7277/AD7278 t 8 1.4V ...
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... AD7276/AD7277/AD7278 TIMING EXAMPLES For the AD7276 brought high during the 14 edge after the two leading zeros and 12 bits of the conversion have been provided, the part can achieve the fastest throughput rate, 3 MSPS brought high during the 16 edge after the two leading zeros and 12 bits of the conversion and two trailing zeros have been provided, a throughput rate of 2 ...
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... device reliability. −0 0 ±10 mA ESD CAUTION −40°C to +125°C −65°C to +150°C 150°C 230°C/W 92°C/W 205.9°C/W 43.74°C/W 255°C 260°C 1.5 kV Rev Page AD7276/AD7277/AD7278 ...
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... SCLK input. The data stream from the AD7276 consists of two leading zeros followed by 12 bits of conversion data and two trailing zeros, provided MSB first. The data stream from the AD7277 consists of two leading zeros followed by 10 bits of conversion data and four trailing zeros, provided MSB first. The data stream from the AD7278 consists of two leading zeros followed by 8 bits of conversion data and six trailing zeros, provided MSB first ...
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... Figure 10. AD7276 Dynamic Performance at 3 MSPS, Input Tone = 1 MHz –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 FREQUENCY (kHz) Figure 11. AD7277 Dynamic Performance at 3 MSPS, Input Tone = 1 MHz 72.5 72.0 71.5 71 2.35V DD 70.5 70.0 69.5 69.0 68.5 68.0 67.5 ...
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... AD7276/AD7277/AD7278 –50 – 100Ω –60 IN –65 –70 R –75 –80 –85 –90 100 INPUT FREQUENCY (kHz) Figure 16. THD vs. Analog Input Frequency at 3 MSPS for Various Source Impedances, SCLK Frequency = 48 MHz, Supply Voltage = 3 V 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 500 1000 1500 ...
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... The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. For the AD7276/ AD7277/AD7278, the endpoints of the transfer function are zero scale at 0.5 LSB below the first code transition and full scale at 0.5 LSB above the last code transition. ...
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... AD7278 are followed by four and six trailing zeros, respectively. Alternatively, because the supply current required by the AD7276/ AD7277/AD7278 is so low, a precision reference can be used as the supply source for the AD7276/AD7277/AD7278. A REF19x voltage reference (REF193 for 3 V) can be used to supply the required voltage to the ADC (see Figure 22). This configuration is especially useful if the power supply is noisy or the system’ ...
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... Instead, the digital inputs applied to the AD7276/AD7277/ AD7278 can and are not restricted by the V limit of the analog inputs. For example, if the AD7276/AD7277/ AD7278 are operated with used on the digital inputs. However important to note ...
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... For the AD7276, a minimum of 14 serial clock cycles are required to complete the conversion and access the complete conversion result. For the AD7277 and AD7278, a minimum of 12 and 10 serial clock cycles are required to complete the conversion and to access the complete conversion result, respectively. ...
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... SCLK edge, following the falling edge of Figure 26 When power supplies are first applied to the AD7276/AD7277/ AD7278, the ADC can power up in either of the power-down modes or in normal mode. Because of this best to allow a dummy cycle to elapse to ensure that the part is fully powered up before attempting a valid conversion ...
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... AD7276/AD7277/AD7278 THE PART BEGINS TO POWER SCLK A SDATA INVALID DATA THE PART ENTERS PARTIAL POWER-DOWN SCLK INVALID DATA SDATA THE PART BEGINS TO POWER SCLK SDATA INVALID DATA THE PART IS FULLY POWERED UP, SEE THE POWER- UP TIMES SECTION Figure 26. Exiting Partial Power-Down Mode ...
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... V). If the power-up time is one DD dummy cycle, that is, 333 ns, and the remaining conversion time is 290 ns, then the AD7276/AD7277/AD7278 can be said to dissipate 12.6 mW for 623 ns during each conversion cycle. If the throughput rate is 200 kSPS, then the cycle time is 5 μs and the average power dissipated during each cycle is 623/5,000 × ...
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... Figure 33 at Point B. If the rising edge of CS occurs before 12 SCLKs elapse, the conversion is terminated and the SDATA line goes back into three-state SCLKs are considered in the cycle, the AD7277 clocks out four trailing zeros for the last four bits and SDATA returns to three-state on the 16 falling edge, as shown in Figure 33 ...
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... Figure 32. AD7276 Serial Interface Timing Diagram 16 SCLK Cycle CS t CONVERT SCLK SDATA Z ZERO DB9 DB8 THREE- STATE 2 LEADING ZEROS Figure 33. AD7277 Serial Interface Timing Diagram CS t CONVERT SCLK SDATA Z ZERO DB7 DB6 THREE- STATE 2 LEADING ZEROS Figure 34 ...
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... This allows a value for t , satisfying the minimum QUIET requirement of 4 ns. MICROPROCESSOR INTERFACING AD7276/AD7277/AD7278-to-ADSP-BF53x The ADSP-BF53x family of DSPs interfaces directly to the AD7276/AD7277/AD7278 without requiring glue logic. The SPORT0 Receive Configuration 1 Register should be set up as outlined in Table 9. AD7276/ ADSP-BF53x* AD7277/ SPORT0 ...
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... However, the analog ground plane should be allowed to run under the AD7276/AD7277/AD7278 to avoid noise coupling. The power supply lines to the AD7276/ AD7277/AD7278 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. ...
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... AD7276/AD7277/AD7278 OUTLINE DIMENSIONS 1.60 BSC PIN 1 INDICATOR * 0.90 0.87 0.84 0.10 MAX 3.20 3.00 2.80 IDENTIFIER 0.95 0.85 0.75 COPLANARITY 2.90 BSC 2.80 BSC 0.95 BSC 1.90 BSC 0.20 * 1.00 MAX 0.08 8° SEATING 0.50 PLANE 4° 0.30 0° * COMPLIANT TO JEDEC STANDARDS MO-193-AA WITH THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS. Figure 37. 6-Lead Thin Small Outline Transistor Package [TSOT] (UJ-6) Dimensions shown in millimeters 3 ...
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... AD7277BUJZ-500RL7 −40°C to +125°C AD7277BUJZ-REEL7 −40°C to +125°C AD7277ARMZ −40°C to +125°C AD7277ARMZ-RL −40°C to +125°C AD7277AUJZ-500RL7 −40°C to +125°C AD7277AUJZ-RL7 −40°C to +125°C AD7278BRMZ −40°C to +125°C AD7278BRMZ-REEL −40°C to +125°C AD7278BUJZ-500RL7 − ...
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... AD7276/AD7277/AD7278 NOTES ©2005–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04903-0-5/11(C) Rev Page ...