AD7762 Analog Devices, AD7762 Datasheet - Page 24

• Manufacturer Part Number: AD7762
• Description: Parallel Interface, 625 kSPS, 24-Bit Sigma-Delta A/D Converter
• Manufacturer: Analog Devices

Specifications of AD7762

• Resolution (bits): 24bit
• # Chan: 1
• Sample Rate: 40MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: (1.6Vref) p-p,4 V p-p,6.5 V p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: QFP

AD7762
STATUS REGISTER (READ ONLY)
MSB
PART 1
Table 17.
Bit
15, 14
13 to 11
10
9
8
7
6
5
4
3
2-0
OFFSET REGISTER—ADDRESS 0X0003
Non-bitmapped, Default Value 0x0000
The offset register uses twos complement notation and is scaled such that 0x7FFF (maximum positive value) and 0x8000 (maximum
negative value) correspond to an offset of +0.78125% and −0.78125%, respectively. Offset correction is applied after any gain correction.
Using the default gain value of 1.25 and assuming a reference voltage of 4.096V, the offset correction range is approximately ±25 mV.
GAIN REGISTER—ADDRESS 0X0004
Non-bitmapped, Default Value 0xA000
The gain register is scaled such that 0x8000 corresponds to a gain of 1.0. The default value of this register is 1.25 (0xA000). This gives a
full-scale digital output when the input is at 80% of V
OVERRANGE REGISTER—ADDRESS 0X0005
Non-bitmapped, Default Value 0xCCCC
The overrange register value is compared with the output of the first decimation filter to obtain an overload indication with minimum
propagation delay. This is prior to any gain scaling or offset adjustment. The default value is 0xCCCC which corresponds to 80% of V
(the maximum permitted analog input voltage). Assuming V
approximately 6.55 V p-p differential. Note that the overrange bit is also set immediately if the analog input voltage exceeds 100% of V
for more than four consecutive samples at the modulator rate.
PART 0
Mnemonic
PART1:0
DIE2:0
DVALID
LPWR
OVR
DL OK
Filter OK
U Filter
BYP F3
1
DEC2:0
DIE 2
Comment
Part Number. These bits are constant for the AD7762.
Die Number. These bits reflect the current AD7762 die number for identification purposes within a system.
Data Valid. This bit corresponds to the DVALID bit in the status word output in the second 16-bit read operation.
Low Power. If the AD7762 is operating in low power mode, this bit is set to 1.
If the current analog input exceeds the current overrange threshold, this bit is set.
When downloading a user filter to the AD7762, a checksum is generated. This checksum is compared to the one
downloaded following the coefficients. If these checksums agree, this bit is set.
When a user-defined filter is in use, a checksum is generated when the filter coefficients pass through the filter. This
generated checksum is compared to the one downloaded. If they match, this bit is set.
If a user-defined filter is in use, this bit is set.
Bypass Filter 3. If Filter 3 is bypassed by setting the relevant bit in Control Register 1, this bit is also set.
This bit is always set.
Decimation Rate. These correspond to the bits set in Control Register 1.
DIE 1
DIE 0
DVALID
REF
LPWR
. This ties in with the maximum analog input range of ±80% of V
Rev. 0 | Page 24 of 28
REF
OVR
= 4.096 V, the bit is then set when the input voltage exceeds
DL OK
Filter OK
U Filter
BYP F3
1
DEC2
REF
DEC1
p-p.
LSB
DEC0
REF
REF