AD7691 Analog Devices, AD7691 Datasheet - Page 22

• Manufacturer Part Number: AD7691
• Manufacturer: Analog Devices

Specifications of AD7691

• Resolution (bits): 18bit
• # Chan: 1
• Sample Rate: 250kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: CSP,SOP

AD7691
CHAIN MODE WITHOUT BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7691s on
a 3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7691s is shown in
Figure 43, and the corresponding timing is given in Figure 44.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the busy indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
SDO
ACQUISITION
SDI
A
t
HSCKCNV
= SDI
CNV
SCK
SDO
A
= 0
B
B
CONVERSION
t
SSCKCNV
t
CONV
t
EN
SDI
t
t
HSDO
DSDO
AD7691
Figure 44. Chain Mode Without Busy Indicator Serial Interface Timing
Figure 43. Chain Mode Without Busy Indicator Connection Diagram
CNV
SCK
A
D
D
1
A
B
17
17
t
SSDISCK
SDO
D
D
A
B
2
16
16
D
D
3
A
B
15
15
Rev. B | Page 22 of 28
t
SCKL
SDI
t
HSDISCK
16
AD7691
CNV
SCK
B
t
D
D
17
CYC
A
B
readback. When the conversion is complete, the MSB is output
onto SDO and the AD7691 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are clocked by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 18 × N clocks are required to
read back the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge can allow a faster reading
rate and, consequently, more AD7691s in the chain, provided
the digital host has an acceptable hold time. The maximum
conversion rate may be reduced due to the total readback time.
1
1
ACQUISITION
t
SDO
SCK
t
t
SCKH
D
D
ACQ
18
A
B
0
0
D
19
A
17
CONVERT
DATA IN
CLK
D
20
A
DIGITAL HOST
16
34
D
35
A
1
D
36
A
0