AD7691 Analog Devices, AD7691 Datasheet - Page 21

• Manufacturer Part Number: AD7691
• Manufacturer: Analog Devices

Specifications of AD7691

• Resolution (bits): 18bit
• # Chan: 1
• Sample Rate: 250kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: CSP,SOP

CS MODE, 4-WIRE WITH BUSY INDICATOR
This mode is normally used when a single AD7691 is connected
to an SPI-compatible digital host with an interrupt input, and it
is desired to keep CNV, which is used to sample the analog
input, independent of the signal used to select the data reading.
This requirement is particularly important in applications
where low jitter on CNV is desired.
The connection diagram is shown in Figure 41, and the
corresponding timing is given in Figure 42.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time elapses and then held low for the maximum possible
conversion time to guarantee the generation of the busy signal
indicator. When the conversion is complete, SDO goes from
high impedance to low impedance. With a pull-up on the SDO
ACQUISITION
CNV
SCK
SDO
SDI
t
SSDICNV
t
HSDICNV
CONVERSION
t
CONV
Figure 42. 4-Wire CS Mode with Busy Indicator Serial Interface Timing
t
EN
1
Rev. B | Page 21 of 28
t
t
HSDO
DSDO
D17
2
t
CYC
line, this transition can be used as an interrupt signal to initiate
the data readback controlled by the digital host. The AD7691
then enters the acquisition phase and powers down. The data
bits are clocked out, MSB first, by subsequent SCK falling edges.
The data is valid on both SCK edges. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge can allow a faster reading rate, provided it has an
acceptable hold time. After the optional 19
or SDI going high, whichever occurs first, SDO returns to high
impedance.
D16
3
ACQUISITION
Figure 41. 4-Wire CS Mode with Busy Indicator Connection Diagram
t
ACQ
t
SCKL
t
SCKH
17
SDI
AD7691
t
SCK
CNV
SCK
18
D1
SDO
19
D0
VIO
47kΩ
t
DIS
CS1
CONVERT
DATA IN
IRQ
CLK
DIGITAL HOST
th
SCK falling edge,
AD7691