AD7142 Analog Devices, AD7142 Datasheet - Page 39

• Manufacturer Part Number: AD7142
• Description: Programmable Controller for Capacitance Touch Sensors
• Manufacturer: Analog Devices

Specifications of AD7142

• Resolution (bits): 16bit
• # Chan: 14
• Sample Rate: 250kSPS
• Interface: I²C/Ser 2-Wire,Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: ± 2 pF (Delta C)
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

REGISTER MAP
The AD7142 address space is divided into three different register
banks, referred to as Bank 1, Bank 2, and Bank 3. Figure 59
shows the division of these three banks.
Bank 1 contains control registers, CDC conversion control
registers, interrupt enable registers, interrupt status registers,
CDC 16-bit conversion data registers, device ID registers, and
proximity status registers.
Bank 2 contains the configuration registers used for uniquely
configuring the CIN inputs for each conversion stage. Initialize
the Bank 2 configuration registers immediately after power-up
to obtain valid CDC conversion result data.
ADDR 0x000
ADDR 0x001
ADDR 0x005
ADDR 0x008
ADDR 0x00B
ADDR 0x017
ADDR 0x018
ADDR 0x042
ADDR 0x7F0
ADDR 0x043
CDC 16-BIT CONVERSION DATA
PROXIMITY STATUS REGISTER
CALIBRATION AND SET UP
INVALID DO NOT ACCESS
INVALID DO NOT ACCESS
DEVICE ID REGISTER
INTERRUPT STATUS
INTERRUPT ENABLE
REGISTER BANK 1
SET UP CONTROL
(12 REGISTERS)
(4 REGISTERS)
(3 REGISTERS)
(3 REGISTERS)
(1 REGISTER)
Figure 59. Layout of Bank 1 Registers, Bank 2 Registers, and Bank 3 Registers
ADDR 0x0A0
ADDR 0x0A8
ADDR 0x0B0
ADDR 0x0B8
ADDR 0x0C0
ADDR 0x0C8
ADDR 0x0D0
ADDR 0x0D8
ADDR 0x080
ADDR 0x088
ADDR 0x090
ADDR 0x098
Rev. A | Page 39 of 72
STAGE10 CONFIGURATION
STAGE11 CONFIGURATION
STAGE0 CONFIGURATION
STAGE1 CONFIGURATION
STAGE2 CONFIGURATION
STAGE3 CONFIGURATION
STAGE4 CONFIGURATION
STAGE5 CONFIGURATION
STAGE6 CONFIGURATION
STAGE7 CONFIGURATION
STAGE8 CONFIGURATION
STAGE9 CONFIGURATION
REGISTER BANK 2
(8 REGISTERS)
(8 REGISTERS)
(8 REGISTERS)
(8 REGISTERS)
(8 REGISTERS)
(8 REGISTERS)
(8 REGISTERS)
(8 REGISTERS)
(8 REGISTERS)
(8 REGISTERS)
(8 REGISTERS)
(8 REGISTERS)
Bank 3 registers contain the results of each conversion stage.
These registers automatically update at the end of each conversion
sequence. Although these registers are primarily used by the
AD7142 internal data processing, they are accessible by the host
processor for additional external data processing, if desired.
Default values are undefined for Bank 2 registers and Bank 3
registers until after power-up and configuration of the Bank 2
registers.
ADDR 0x0E0
ADDR 0x0A0
ADDR 0x0A8
ADDR 0x0B0
ADDR 0x0B8
ADDR 0x0C0
ADDR 0x0C8
ADDR 0x0D0
ADDR 0x088
ADDR 0x090
ADDR 0x098
ADDR 0x28F
REGISTER BANK 3
STAGE10 RESULTS
STAGE11 RESULTS
STAGE0 RESULTS
STAGE1 RESULTS
STAGE2 RESULTS
STAGE3 RESULTS
STAGE4 RESULTS
STAGE5 RESULTS
STAGE6 RESULTS
STAGE7 RESULTS
STAGE8 RESULTS
STAGE9 RESULTS
(36 REGISTERS)
(36 REGISTERS)
(36 REGISTERS)
(36 REGISTERS)
(36 REGISTERS)
(36 REGISTERS)
(36 REGISTERS)
(36 REGISTERS)
(36 REGISTERS)
(36 REGISTERS)
(36 REGISTERS)
(36 REGISTERS)
AD7142