AD7142 Analog Devices, AD7142 Datasheet
AD7142
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AD7142 Summary of contents
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... C-compatible serial interface. Both parts have an interrupt output, as well as a general-purpose input/ output (GPIO). The AD7142 and AD7142-1 are available in a 32-lead × LFCSP_VQ and operate from a 2 3.6 V supply. The operating current consumption is less than 1 mA, falling to 50 μA in low power mode (conversion interval of 400 ms). ...
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... Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 3 Specifications..................................................................................... 4 SPI Timing Specifications (AD7142)......................................... Timing Specifications (AD7142-1) ..................................... 7 Absolute Maximum Ratings............................................................ 8 ESD Caution.................................................................................. 8 Pin Configurations and Function Descriptions ........................... 9 Typical Performance Characteristics ........................................... 10 Theory of Operation ...................................................................... 12 Capacitance Sensing Theory..................................................... 12 Operating Modes........................................................................ 13 Capacitance Sensor Input Configuration.................................... 14 CIN Input Multiplexer Setup ...
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... Inserted Figure 37 and Table 13 ....................................................25 Deleted Figure 42 ............................................................................29 Changes to C Output Section ...............................................30 SHIELD Changes to Figure 55 ......................................................................36 Changes to Power-up Sequence Section ......................................37 Changes to Figure 58 ......................................................................38 Changes to Table 21 ........................................................................42 Changes to Table 24 ........................................................................43 Changes to Table 25 ........................................................................44 Changes to Table 29 ........................................................................48 Changes to Table 31 ........................................................................49 6/06—Revision 0: Initial Version Rev Page AD7142 ...
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... AD7142 SPECIFICATIONS 2 3 − +85°C, unless otherwise noted Table 1. Parameter CAPACITANCE-TO-DIGITAL CONVERTER Update Rate Resolution CIN Input Range 1 No Missing Codes CIN Input Leakage Total Unadjusted Error Output Noise (Peak-to-Peak) Output Noise (RMS) Parasitic Capacitance ...
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... 53.6 61.5 69.4 77.1 72 87.2 102 116.3 43.6 47.7 51.8 55.8 53.1 61.1 68.9 76.7 40.3 43 45.8 48.5 46.7 52.1 57.4 62.7 38.6 40.7 42.7 44.8 43.4 47.5 51.5 55.6 Rev Page 66.5 72.8 79.1 85.2 99.3 111 122.3 133.4 144.2 38.6 42 45.4 48.7 52 59.6 66.1 72.4 78.7 84.9 31.2 33.5 35.8 38.1 40.4 45.6 50 54.4 58.8 63.1 27.5 29.2 31 32.7 34.4 38.4 41.8 45.2 48.5 51 84.7 92.2 99.6 106.8 113.9 130.2 143.7 156.8 169.5 181.8 59.8 63.7 67.6 71.5 75.4 84.3 91.8 99.1 106.4 113.6 51.2 53.9 56.5 59.2 61.8 67.9 73.1 78.2 83.3 88.3 46.8 48.8 50.9 52.9 54.9 59.5 63.5 67.4 71.3 75.2 AD7142 11 12 91.3 97.3 154.7 164.9 55.3 58 42.6 44.8 67.4 71.6 36.1 37.8 55.1 58 121 127.9 193.8 205.5 79.2 83 120.6 127.5 64.5 67.1 93.3 98.2 56.9 58.9 79 82.8 ...
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... AD7142 SPI TIMING SPECIFICATIONS (AD7142 −40°C to +85° DRIVE compliance. All input signals are specified with t Table 4. SPI Timing Specifications Parameter Limit MIN MAX f 5 SCLK ...
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... I C TIMING SPECIFICATIONS (AD7142- −40°C to +85° DRIVE compliance. All input signals timed from a voltage level of 1 Table Timing Specifications Parameter Limit f 400 SCLK 100 4 t 300 300 ...
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... AD7142 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter AV to AGND DGND CC CC Analog Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND Input Current to Any Pin Except 1 Supplies ESD Rating (Human Body Model) Operating Temperature Range Storage Temperature Range Junction Temperature ...
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... Digital Ground Serial Interface Operating Voltage Supply. DRIVE 21 SDO (AD7142) SPI Serial Data Output. 2 SDA (AD7142- SDI (AD7142) SPI Serial Data Input. 2 ADD0 (AD7142- SCLK Clock Input for Serial Interface (AD7142) SPI Chip Select Signal. 2 ADD1 (AD7142-1) I ...
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... AD7142 TYPICAL PERFORMANCE CHARACTERISTICS 1000 980 DEVICE 1 960 DEVICE 3 940 920 DEVICE 2 900 880 860 840 820 2.7 2.8 2.9 3.0 3.1 3.2 V (V) CC Figure 8. Supply Current vs. Supply Voltage ( 180 LP_CONV_DELAY = 200ms 160 140 120 LP_CONV_DELAY = 400ms 100 80 LP_CONV_DELAY = 600ms 60 LP_CONV_DELAY = 800ms 40 2.7 2.8 2.9 3.0 3.1 3.2 V (V) CC Figure 9 ...
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... FREQUENCY (Hz) Figure 16. Power Supply Sine Wave Rejection 180 160 140 120 100 100 1k 10k 100k SQUARE WAVE FREQUENCY (Hz) Figure 17. Power Supply Square Wave Rejection AD7142 10M 300mV 200mV 100mV 50mV 25mV 1M 10M ...
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... The internal circuitry consists of a 16-bit, ∑-Δ con- verter that converts a capacitive input signal into a digital value. There are 14 input pins on the AD7142 and AD7142-1, CIN0 to CIN13. A switch matrix routes the input signals to the CDC. The result of each capacitance-to-digital conversion is stored in on-chip registers ...
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... CONVERSION SEQUENCE EVERY LP_CONV_DELAY ms UPDATE COMPENSATION LOGIC DATA PATH The time taken for the AD7142 to go from a full power state to a reduced power state, once the user stops touching the external sensors, is configurable. The PWR_DWN_TIMEOUT bits, in Ambient Compensation Ctrl 0 Register, at Address 0x002, control the length of time the AD7142 takes before going into the reduced power state, once the sensors are not touched ...
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... CDC. The AD7142 has an on-chip multiplexer to route the input signals from each pin to the input of the converter. Each input pin can be tied to either the negative or the positive input of the ...
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... Do not use this setting. The decimation process on the AD7142 is an averaging process where a number of samples are taken and the averaged result is output. Due to the architecture of the digital filter employed, the amount of samples taken (per stage) is equal to 3 times the decimation rate × ...
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... CIN12 CIN13 Figure 24. CDC Conversion Stages The number of required conversion stages depends completely on the number of sensors attached to the AD7142. Figure 25 shows how many conversion stages are required for each sensor, and how many inputs each sensor requires to the AD7142. AD7142 SEQUENCER ...
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... The host processes the data readback from these registers using a software algorithm, to determine position information. In addition to the results registers in the Bank 3 registers, the AD7142 provides the 16-bit CDC output data directly, starting at Address 0x00B of Bank 1. Reading back the CDC 16-bit conversion data register allows for customer-specific application data processing ...
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... This means the ambient value stored on the AD7142 no longer represents the actual ambient value. In this case, even when the user has left the sensor, the proximity flag may still be set. This ...
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... AREA HERE BY PROXIMITY_RECAL _LVL CALDIS CALIBRATION DISABLED RECALIBRATION TIME-OUT t DETERMINED FROM TABLE 10 CONV_FP × FP_PROXIMITY_CNT ×16 t × FP_PROXIMITY_RECAL CONV_FP Rev Page CALDIS CALIBRATION ENABLED t 1718 CALIBRATION ENABLED t RECAL 70 CALIBRATION ENABLED t RECAL_TIMEOUT AD7142 t CONV_FP CONV_LP t CONV_FP ...
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... Determining the FF_SKIP_CNT value is required only once during the initial setup of the capacitance sensor interface. Table 13 shows how FF_SKIP_CNT controls the update rate to the fast FIFO. Recommended value for this setting when using all 12 conversion stages on the AD7142 is FF_SKIP_CNT = 0000 = no samples skipped. Table 13. FF_SKIP_CNT Settings ...
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... PROXIMITY_DETECTION_RATE REGISTER 0x003 STAGE_FF_AVG BANK 3 REGISTERS COMPARATOR 2 AVERAGE – AMBIENT SW1 PROXIMITY_RECAL_LVL REGISTER 0x003 STAGE_SF_AMBIENT BANK 3 REGISTERS Figure 32. AD7142 Proximity Detection and Environmental Calibration Rev Page AD7142 FP_PROXIMITY_CNT LP_PROXIMITY_CNT REGISTER 0x002 REGISTER 0X002 PROXIMITY PROXIMITY TIMING CONTROL LOGIC FP_PROXIMITY_RECAL LP_PROXIMITY_RECAL ...
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... Capacitance sensor output levels are sensitive to temperature, humidity, and in some cases, dirt. The AD7142 achieves optimal and reliable sensor performance by continuously monitoring the CDC ambient levels and correcting for any changes by adjusting the STAGE_HIGH_THRESHOLD and STAGE_LOW_ THRESHOLD register values, as described in Equation 1 and Equation 2 ...
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... Figure 35. Typical Sensor Behavior with Calibration Applied on the Data Path SLOW FIFO As shown in Figure 32, there are a number of FIFOs implemented on the AD7142. These FIFOs are located in Bank 3 of the on-chip memory. The slow FIFOs are used by the on-chip logic to monitor the ambient capacitance level from each sensor ...
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... This algorithm continu- ously monitors the output levels of each sensor and automatically rescales the threshold levels proportionally to the sensor area covered by the user result, the AD7142 maintains optimal threshold and sensitivity levels for all types of users regardless of their finger sizes. ...
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... POS_PEAK_DETECT percentage of the min average, only then is the max average value updated. Used in Equation 2. An initial value (based on sensor characterization) is programmed into this register at start up. The AD7142 on chip calibration algorithm automatically updates this register based on the amount of sensor drift due to changing ambient conditions. Set to 80% of the STAGE_OFFSET_LOW_CLAMP value. ...
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... Clearing this bit to 0 disables the conversion complete interrupt for that stage. In normal operation, the AD7142 interrupt is enabled only for the last stage in a conversion sequence. For example, if there are five conversion stages, the conversion complete interrupt for STAGE4 is enabled ...
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... READ THE STAGE0_LOW_LIMIT_INT (ADDRESS 0x008) REGISTER 2. READ THE STAGE5_LOW_LIMIT_INT (ADDRESS 0x008) REGISTER Figure 40. Example of Configuring the Registers for Sensor Interrupt Setup STAGE3 STAGE4 STAGE5 STAGE6 STAGE7 2 STAGE3 STAGE4 STAGE5 STAGE6 STAGE7 4 Rev Page AD7142 STAGE8 STAGE9 STAGE10 STAGE11 3 STAGE8 STAGE9 STAGE10 STAGE11 2 ...
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... AD7142 GPIO INT OUTPUT CONTROL The INT output signal can be controlled by the GPIO pin when the GPIO is configured as an input. The GPIO is configured as an input by setting the GPIO_SETUP bits in the interrupt configuration register to 01. See the GPIO section for more information on how to configure the GPIO. ...
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... Rev Page INT GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 11 INT Behavior Not triggered Asserted when signal on GPIO pin is low Pulses low at low-to-high GPIO transition Not triggered Pulses low at high-to-low GPIO transition Not triggered Asserted when signal on GPIO pin is high Not triggered AD7142 ...
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... GPIO configuration setups. USING THE GPIO TO TURN ON/OFF AN LED The GPIO on the AD7142 can be used to turn on and off LEDs by setting the GPIO as either output high or low. Setting the GPIO output high turns on the LED; setting the GPIO output low turns off the LED ...
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... AD7142 automatically incre- ments the address pointer, and clocks the next data-word into the next register. The AD7142 continues to clock in data on the SDI line until either the master finishes the write transition by pulling CS high, or the address pointer reaches its maximum value. The AD7142 address pointer does not wrap around ...
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... Reading Data A read transaction begins when the master writes the command word to the AD7142 with the read/write bit set to 1. The master then supplies 16 clock pulses per data-word to be read, and the AD7142 clocks out data from the addressed register on the SDO line ...
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... When all data bytes are read or written, a stop condition is established. A stop condition is defined by a low-to-high transition on SDA when SCLK remains high. If the AD7142 encounters a stop condition, it returns to its idle condition, and the address pointer register resets to Address 0x00. ...
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... A read transaction initiated, with the R/ W bit set to 1. Reg. Reg. Reg. The AD7142-1 supplies the upper eight bits of data from the Addr. Addr. Addr. addressed register in the first readback byte, followed by the Bit 2 Bit 1 Bit 0 lower eight bits in the next byte ...
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... ACK = ACKNOWLEDGE BIT ACK = NO ACKNOWLEDGE BIT 2 Figure 52. Example of Sequential I C Write and Readback Operation This allows the AD7142 to be connected directly to processors whose supply voltage is less than the minimum operating 2 C and voltage of the AD7142 without the need for external level- shifters ...
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... AD7142 PCB DESIGN GUIDELINES CAPACITIVE SENSOR BOARD MECHANICAL SPECIFICATIONS Table 18. Parameter Distance from Edge of Any Sensor to Edge of Grounded Metal Object 1 Distance Between Sensor Edges Distance Between Bottom of Sensor Board and Controller Board or Grounded 2 Metal Casing 1 The distance is dependent on the application and the positioning of the switches relative to each other and with respect to the user’s finger positioning and handling. ...
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... POWER-UP SEQUENCE When the AD7142 is powered up, the following sequence is recommended when initially developing the AD7142 and μP serial interface: 1. Turn on the power supplies to the AD7142. 2. Write to the Bank 2 registers at Address 0x080 through Address 0x0DF. These registers are contiguous so a sequential register write sequence can be applied. ...
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... CIN8 6 CIN9 7 8 CIN10 10nF Figure 57. Typical Application Circuit with SPI Interface CIN3 CIN4 2 3 CIN5 4 CIN6 AD7142-1 5 CIN7 CIN8 6 CIN9 7 8 CIN10 10nF Figure 58. Typical Application Circuit with I Rev Page DRIVE AV DV CC, CC 2.2kΩ INT INTERFACE ...
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... REGISTER MAP The AD7142 address space is divided into three different register banks, referred to as Bank 1, Bank 2, and Bank 3. Figure 59 shows the division of these three banks. Bank 1 contains control registers, CDC conversion control registers, interrupt enable registers, interrupt status registers, CDC 16-bit conversion data registers, device ID registers, and proximity status registers ...
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... AD7142 DETAILED REGISTER DESCRIPTIONS BANK 1 REGISTERS All addresses and default values are expressed in hexadecimal. Table 19. PWR_CONTROL Register Address Data Bit Default Value 0x000 [1:0] 0 [3:2] 0 [7:4] 0 [9:8] 0 [10] 0 [11] 0 [12] 0 [13] 0 [15:14] 0 Type Name Description R/W POWER_MODE Operating modes 00 = full power mode (normal operation, CDC ...
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... STAGE9 calibration enable 0 = disable 1 = enable STAGE10 calibration enable 0 = disable 1 = enable STAGE11 calibration enable 0 = disable 1 = enable Full power mode skip control 00 = skip 3 samples 01 = skip 7 samples 10 = skip 15 samples 11 = skip 31 samples Low power mode skip control 00 = use all samples 01 = skip 1 sample 10 = skip 2 samples 11 = skip 3 samples AD7142 ...
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... AD7142 Table 21. AMB_COMP_CTRL0 Register Address Data Bit Default Value 0x002 [3:0] 0 [7:4] F [11:8] F [13:12] 0 [14] 0 [15] 0 Table 22. AMB_COMP_CTRL1 Register Default Address Data Bit Value Type 0x003 [7:0] 64 R/W [13:8] 1 [15:14] 0 Table 23. AMB_COMP_CTRL2 Register Default Address Data Bit Value Type 0x004 [9:0] 3FF R/W [15:10] 3F Type Name R/W FF_SKIP_CNT FP_PROXIMITY_CNT LP_PROXIMITY_CNT ...
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... INT asserted if STAGE11 low threshold is exceeded GPIO setup 00 = disable GPIO pin 01 = configure GPIO as an input 10 = configure GPIO as an active low output 11 = configure GPIO as an active high output GPIO input configuration 00 = triggered on negative level 01 = triggered on positive edge 10 = triggered on negative edge 11 = triggered on positive level AD7142 ...
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... AD7142 Table 25. STAGE_HIGH_INT_EN Register Address Data Bit Default Value 0x006 [0] 0 [1] 0 [2] 0 [3] 0 [4] 0 [5] 0 [6] 0 [7] 0 [8] 0 [9] 0 [10] 0 [11] 0 [15:12] Type Name R/W STAGE0_HIGH_INT_EN STAGE1_HIGH_INT_EN STAGE2_HIGH_INT_EN STAGE3_HIGH_INT_EN STAGE4_HIGH_INT_EN STAGE5_HIGH_INT_EN STAGE6_HIGH_INT_EN STAGE7_HIGH_INT_EN STAGE8_HIGH_INT_EN STAGE9_HIGH_INT_EN STAGE10_HIGH_INT_EN STAGE11_HIGH_INT_EN Unused Rev Page Description ...
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... INT asserted at completion of STAGE9 conversion STAGE10 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE10 conversion STAGE11 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE11 conversion Interrupt control when GPIO input pin changes level 0 = disabled 1 = enabled Set unused register bits = 0 AD7142 ...
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... AD7142 Table 27. STAGE_LOW_LIMIT_INT Register Address Data Bit Default Value 0x008 [0] 0 [1] 0 [2] 0 [3] 0 [4] 0 [5] 0 [6] 0 [7] 0 [8] 0 [9] 0 [10] 0 [11] 0 [15:12] 1 Registers self-clear to 0 after readback, provided that the limits are not exceeded. 1 Type Name R STAGE0_LOW_LIMIT_INT STAGE1_LOW_LIMIT_INT STAGE2_LOW_LIMIT_INT STAGE3_LOW_LIMIT_INT STAGE4_LOW_LIMIT_INT ...
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... STAGE9 CDC conversion high limit interrupt result 1 = indicates STAGE9_HIGH_THRESHOLD value was exceeded STAGE10 CDC conversion high limit interrupt result 1 = indicates STAGE10_HIGH_THRESHOLD value was exceeded STAGE11 CDC conversion high limit interrupt result 1 = indicates STAGE11_HIGH_THRESHOLD value was exceeded Set unused register bits = 0 AD7142 ...
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... AD7142 Table 29. STAGE_COMPLETE_LIMIT_INT Register Default Address Data Bit Value Type 0x00A [ [1] 0 [2] 0 [3] 0 [4] 0 [5] 0 [6] 0 [7] 0 [8] 0 [9] 0 [10] 0 [11] 0 [12] 0 [15:13] 1 Registers self-clear to 0 after readback, provided that the limits are not exceeded. Table 30. CDC 16-Bit Conversion Data Registers ...
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... R [11 [15:0] Name Description REVISION_CODE AD7142 revision code DEVID AD7142 device ID = 1110 0110 0010 Name Description STAGE0_PROXIMITY_STATUS STAGE0 proximity status register 1 = indicates proximity has been detected on STAGE0 STAGE1_PROXIMITY_STATUS STAGE1 proximity status register 1 = indicates proximity has been detected on STAGE1 STAGE2_PROXIMITY_STATUS STAGE2 proximity status register ...
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... AD7142 BANK 2 REGISTERS All address values are expressed in hexadecimal. Table 33. STAGE0 Configuration Registers Default Address Data Bit Value Type 0x080 [15:0] X R/W 0x081 [15:0] X R/W 0x082 [15:0] X R/W 0x083 [15:0] X R/W 0x084 [15:0] X R/W 0x085 [15:0] X R/W 0x086 [15:0] X R/W 0x087 [15:0] X R/W Table 34. STAGE1 Configuration Registers Default Address Data Bit Value Type 0x088 [15:0] X R/W 0x089 [15:0] X R/W 0x08A [15:0] X R/W 0x08B ...
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... STAGE5_AFE_OFFSET STAGE5 AFE offset control (see Table 47) STAGE5_SENSITIVITY STAGE5 sensitivity control (see Table 48) STAGE5_OFFSET_LOW STAGE5 initial offset low value STAGE5_OFFSET_HIGH STAGE5 initial offset high value STAGE5_OFFSET_HIGH_CLAMP STAGE5 offset high clamp value STAGE5_OFFSET_LOW_CLAMP STAGE5 offset low clamp value Rev Page AD7142 ...
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... AD7142 Table 39. STAGE6 Configuration Registers Default Address Data Bit Value Type 0x0B0 [15:0] X R/W 0x0B1 [15:0] X R/W 0x0B2 [15:0] X R/W 0x0B3 [15:0] X R/W 0x0B4 [15:0] X R/W 0x0B5 [15:0] X R/W 0x0B6 [15:0] X R/W 0x0B7 [15:0] X R/W Table 40. STAGE7 Configuration Registers Default Address Data Bit Value Type 0x0B8 [15:0] X R/W 0x0B9 [15:0] X R/W 0x0BA [15:0] X R/W 0x0BB [15:0] X R/W 0x0BC [15:0] X R/W 0x0BD [15:0] X R/W 0x0BE [15:0] X R/W 0x0BF [15:0] X R/W Table 41. STAGE8 Configuration Registers ...
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... STAGE11_AFE_OFFSET STAGE11_SENSITIVITY STAGE11_OFFSET_LOW STAGE11_OFFSET_HIGH STAGE11_OFFSET_HIGH_CLAMP STAGE11_OFFSET_LOW_CLAMP Rev Page AD7142 Description STAGE10 CIN(6:0) connection setup (see Table 45) STAGE10 CIN(13:7) connection setup (see Table 46) STAGE10 AFE offset control (see Table 47) STAGE10 sensitivity control (see Table 48) STAGE10 initial offset low value STAGE10 initial offset high value ...
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... AD7142 Table 45. STAGEX Detailed CIN (0:6) Connection Setup Description ( 11) Default Data Bit Value Type Name [1:0] X R/W CIN0_CONNECTION_SETUP [3:2] X R/W CIN1_CONNECTION_SETUP [5:4] X R/W CIN2_CONNECTION_SETUP [7:6] X R/W CIN3_CONNECTION_SETUP [9:8] X R/W CIN4_CONNECTION_SETUP [11:10] X R/W CIN5_CONNECTION_SETUP [13:12] X R/W CIN6_CONNECTION_SETUP [15:14] X Unused Description CIN0 connection setup 00 = CIN0 not connected to CDC inputs 01 = CIN0 connected to CDC negative input 10 = CIN0 connected to CDC positive input ...
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... CIN13 not connected to CDC inputs 01 = CIN13 connected to CDC negative input 10 = CIN13 connected to CDC positive input 11 = CIN13 connected to BIAS (connect unused CIN inputs) NEG_AFE_OFFSET_DISABLE Negative AFE offset enable control 0 = enable 1 = disable POS_AFE_OFFSET_DISABLE Positive AFE offset enable control 0 = enable 1 = disable Rev Page AD7142 ...
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... AD7142 Table 47. STAGEX Detailed Offset Control Description ( 11) Default Data Bit Value Type Name [6:0] X R/W NEG_AFE_OFFSET [7] X R/W NEG_AFE_OFFSET_SWAP [14:8] X R/W POS_AFE_OFFSET [15] X R/W POS_AFE_OFFSET_SWAP Table 48. STAGEX Detailed Sensitivity Control Description ( 11) Default Data Bit Value Type Name [3:0] X R/W NEG_THRESHOLD_SENSITIVITY [6:4] X R/W NEG_PEAK_DETECT [7] X R/W Unused [11:8] X R/W POS_THRESHOLD_SENSITIVITY [14:12] X R/W POS_PEAK_DETECT ...
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... STAGE0 minimum value FIFO WORD1 STAGE0_MIN_WORD2 STAGE0 minimum value FIFO WORD2 STAGE0_MIN_WORD3 STAGE0 minimum value FIFO WORD3 STAGE0_MIN_AVG STAGE0 average minimum FIFO value STAGE0_LOW_THRESHOLD STAGE0 low threshold value STAGE0_MIN_TEMP STAGE0 temporary minimum value Unused Set unused register bits = 0 Rev Page AD7142 ...
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... AD7142 Table 50. STAGE1 Results Registers Default Address Data Bit Value Type 0x104 [15:0] X R/W 0x105 [15:0] X R/W 0x106 [15:0] X R/W 0x107 [15:0] X R/W 0x108 [15:0] X R/W 0x109 [15:0] X R/W 0x10A [15:0] X R/W 0x10B [15:0] X R/W 0x10C [15:0] X R/W 0x10D [15:0] X R/W 0x10E [15:0] X R/W 0x10F [15:0] X R/W 0x110 [15:0] X R/W 0x111 [15:0] X R/W 0x112 [15:0] X R/W 0x113 [15:0] X R/W 0x114 [15:0] X R/W 0x115 [15:0] X R/W 0x116 [15:0] X R/W 0x117 [15:0] X R/W 0x118 [15:0] X R/W 0x119 [15:0] X R/W 0x11A [15:0] X R/W 0x11B [15:0] X R/W 0x11C [15:0] X R/W 0x11D [15:0] X R/W 0x11E [15:0] X R/W 0x11F [15:0] X R/W 0x120 [15:0] X R/W 0x121 ...
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... STAGE2 minimum value FIFO WORD1 STAGE2_MIN_WORD2 STAGE2 minimum value FIFO WORD2 STAGE2_MIN_WORD3 STAGE2 minimum value FIFO WORD3 STAGE2_MIN_AVG STAGE2 average minimum FIFO value STAGE2_LOW_THRESHOLD STAGE2 low threshold value STAGE2_MIN_TEMP STAGE2 temporary minimum value Unused Set unused register bits = 0 Rev Page AD7142 ...
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... AD7142 Table 52. STAGE3 Results Registers Default Address Data Bit Value Type 0x14C [15:0] X R/W 0x14D [15:0] X R/W 0x14E [15:0] X R/W 0x14F [15:0] X R/W 0x150 [15:0] X R/W 0x151 [15:0] X R/W 0x152 [15:0] X R/W 0x153 [15:0] X R/W 0x154 [15:0] X R/W 0x155 [15:0] X R/W 0x156 [15:0] X R/W 0x157 [15:0] X R/W 0x158 [15:0] X R/W 0x159 [15:0] X R/W 0x15A [15:0] X R/W 0x15B [15:0] X R/W 0x15C [15:0] X R/W 0x15D [15:0] X R/W 0x15E [15:0] X R/W 0x15F [15:0] X R/W 0x160 [15:0] X R/W 0x161 [15:0] X R/W 0x162 [15:0] X R/W 0x163 [15:0] X R/W 0x164 [15:0] X R/W 0x165 [15:0] X R/W 0x166 [15:0] X R/W 0x167 [15:0] X R/W 0x168 [15:0] X R/W 0x169 ...
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... STAGE4 minimum value FIFO WORD1 STAGE4_MIN_WORD2 STAGE4 minimum value FIFO WORD2 STAGE4_MIN_WORD3 STAGE4 minimum value FIFO WORD3 STAGE4_MIN_AVG STAGE4 average minimum FIFO value STAGE4_LOW_THRESHOLD STAGE4 low threshold value STAGE4_MIN_TEMP STAGE4 temporary minimum value Unused Set unused register bits = 0 Rev Page AD7142 ...
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... AD7142 Table 54. STAGE5 Results Registers Default Address Data Bit Value Type 0x194 [15:0] X R/W 0x195 [15:0] X R/W 0x196 [15:0] X R/W 0x197 [15:0] X R/W 0x198 [15:0] X R/W 0x199 [15:0] X R/W 0x19A [15:0] X R/W 0x19B [15:0] X R/W 0x19C [15:0] X R/W 0x19D [15:0] X R/W 0x19E [15:0] X R/W 0x19F [15:0] X R/W 0x1A0 [15:0] X R/W 0x1A1 [15:0] X R/W 0x1A2 [15:0] X R/W 0x1A3 [15:0] X R/W 0x1A4 [15:0] X R/W 0x1A5 [15:0] X R/W 0x1A6 [15:0] X R/W 0x1A7 [15:0] X R/W 0x1A8 [15:0] X R/W 0x1A9 [15:0] X R/W 0x1AA [15:0] X R/W 0x1AB [15:0] X R/W 0x1AC [15:0] X R/W 0x1AD [15:0] X R/W 0x1AE [15:0] X R/W 0x1AF [15:0] X R/W 0x1B0 [15:0] X R/W 0x1B1 ...
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... STAGE6 minimum value FIFO WORD1 STAGE6_MIN_WORD2 STAGE6 minimum value FIFO WORD2 STAGE6_MIN_WORD3 STAGE6 minimum value FIFO WORD3 STAGE6_MIN_AVG STAGE6 average minimum FIFO value STAGE6_LOW_THRESHOLD STAGE6 low threshold value STAGE6_MIN_TEMP STAGE6 temporary minimum value Unused Set unused register bits = 0 Rev Page AD7142 ...
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... AD7142 Table 56. STAGE7 Results Registers Default Address Data Bit Value Type 0x1DC [15:0] X R/W 0x1DD [15:0] X R/W 0x1DE [15:0] X R/W 0x1DF [15:0] X R/W 0x1E0 [15:0] X R/W 0x1E1 [15:0] X R/W 0x1E2 [15:0] X R/W 0x1E3 [15:0] X R/W 0x1E4 [15:0] X R/W 0x1E5 [15:0] X R/W 0x1E6 [15:0] X R/W 0x1E7 [15:0] X R/W 0x1E8 [15:0] X R/W 0x1E9 [15:0] X R/W 0x1EA [15:0] X R/W 0x1EB [15:0] X R/W 0x1EC [15:0] X R/W 0x1ED [15:0] X R/W 0x1EE [15:0] X R/W 0x1EF [15:0] X R/W 0x1F0 [15:0] X R/W 0x1F1 [15:0] X R/W 0x1F2 [15:0] X R/W 0x1F3 [15:0] X R/W 0x1F4 [15:0] X R/W 0x1F5 [15:0] X R/W 0x1F6 [15:0] X R/W 0x1F7 [15:0] X R/W 0x1F8 [15:0] X R/W 0x1F9 ...
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... STAGE8 minimum value FIFO WORD1 STAGE8_MIN_WORD2 STAGE8 minimum value FIFO WORD2 STAGE8_MIN_WORD3 STAGE8 minimum value FIFO WORD3 STAGE8_MIN_AVG STAGE8 average minimum FIFO value STAGE8_LOW_THRESHOLD STAGE8 low threshold value STAGE8_MIN_TEMP STAGE7 temporary minimum value Unused Set unused register bits = 0 Rev Page AD7142 ...
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... AD7142 Table 58. STAGE9 Results Registers Default Address Data Bit Value Type 0x224 [15:0] X R/W 0x225 [15:0] X R/W 0x226 [15:0] X R/W 0x227 [15:0] X R/W 0x228 [15:0] X R/W 0x229 [15:0] X R/W 0x22A [15:0] X R/W 0x22B [15:0] X R/W 0x22C [15:0] X R/W 0x22D [15:0] X R/W 0x22E [15:0] X R/W 0x22F [15:0] X R/W 0x230 [15:0] X R/W 0x231 [15:0] X R/W 0x232 [15:0] X R/W 0x233 [15:0] X R/W 0x234 [15:0] X R/W 0x235 [15:0] X R/W 0x236 [15:0] X R/W 0x237 [15:0] X R/W 0x238 [15:0] X R/W 0x239 [15:0] X R/W 0x23A [15:0] X R/W 0x23B [15:0] X R/W 0x23C [15:0] X R/W 0x23D [15:0] X R/W 0x23E [15:0] X R/W 0x23F [15:0] X R/W 0x240 [15:0] X R/W 0x241 ...
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... STAGE10 minimum value FIFO WORD1 STAGE10_MIN_WORD2 STAGE10 minimum value FIFO WORD2 STAGE10_MIN_WORD3 STAGE10 minimum value FIFO WORD3 STAGE10_MIN_AVG STAGE10 average minimum FIFO value STAGE10_LOW_THRESHOLD STAGE10 low threshold value STAGE10_MIN_TEMP STAGE10 temporary minimum value Unused Set unused register bits = 0 Rev Page AD7142 ...
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... AD7142 Table 60. STAGE11 Results Registers Default Address Data Bit Value Type 0x26C [15:0] X R/W 0x26D [15:0] X R/W 0x26E [15:0] X R/W 0x26F [15:0] X R/W 0x270 [15:0] X R/W 0x271 [15:0] X R/W 0x272 [15:0] X R/W 0x273 [15:0] X R/W 0x274 [15:0] X R/W 0x275 [15:0] X R/W 0x276 [15:0] X R/W 0x277 [15:0] X R/W 0x278 [15:0] X R/W 0x279 [15:0] X R/W 0x27A [15:0] X R/W 0x27B [15:0] X R/W 0x27C [15:0] X R/W 0x27D [15:0] X R/W 0x27E [15:0] X R/W 0x27F [15:0] X R/W 0x280 [15:0] X R/W 0x281 [15:0] X R/W 0x282 [15:0] X R/W 0x283 [15:0] X R/W 0x284 [15:0] X R/W 0x285 [15:0] X R/W 0x286 [15:0] X R/W 0x287 [15:0] X R/W 0x288 [15:0] X R/W 0x289 ...
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... PLANE ORDERING GUIDE Model Temperature Range AD7142ACPZ-REEL 1 –40°C to +85°C 1 AD7142ACPZ-500RL7 –40°C to +85°C AD7142ACPZ-1REEL 1 –40°C to +85°C 1 AD7142ACPZ-1500RL7 –40°C to +85°C 1 EVAL-AD7142EBZ 1 EVAL-AD7142-1EBZ Pb-free part. 5.00 BSC SQ 0.60 MAX 24 0.50 BSC TOP 4.75 VIEW BSC SQ 0.50 0.40 17 0.30 0.80 MAX 0.65 TYP 0.05 MAX ...
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... AD7142 NOTES Rev Page ...
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... NOTES Rev Page AD7142 ...
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... AD7142 NOTES 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, provided that the system conforms to the I ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...