AD9271 Analog Devices, AD9271 Datasheet - Page 29

• Manufacturer Part Number: AD9271
• Description: Octal LNA/VGA/AAF/ADC and Crosspoint Switch
• Manufacturer: Analog Devices

Specifications of AD9271

• Resolution (bits): 12bit
• # Chan: 8
• Sample Rate: 50MSPS
• Interface: LVDS,Ser
• Analog Input Type: SE-Uni
• Ain Range: 0.25 V p-p,0.32 V p-p,0.4 V p-p
• Adc Architecture: Pipelined
• Pkg Type: QFP

In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter. IF undersampling applications
are particularly sensitive to jitter (see Figure 59).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9271.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources, such as the Valpey Fisher VFAC3 series.
If the clock is generated from another type of source (by gating,
dividing, or other methods), it should be retimed by the
original clock during the last step.
Refer to the AN-501 Application Note and the AN-756
Application Note for more in-depth information about how
jitter performance relates to ADCs (visit www.analog.com).
Power Dissipation and Power-Down Mode
As shown in Figure 61, the power dissipated by the AD9271 is
proportional to its sample rate. The digital power dissipation
does not vary much because it is determined primarily by the
DRVDD supply and bias current of the LVDS output drivers
(Figure 60).
130
120
110
100
90
80
70
60
50
40
30
800
700
600
500
400
300
200
100
1
0
10 BITS
8 BITS
0
RMS CLOCK JITTER REQUIREMENT
Figure 60. Supply Current vs. f
Figure 59. Ideal SNR vs. Input Frequency and Jitter
I
I
AVDD
AVDD
, 50MSPS SPEED GRADE
, 40MSPS SPEED GRADE
10
ANALOG INPUT FREQUENCY (MHz)
SAMPLING FREQUENCY (MSPS)
10
I
AVDD
20
, 25MSPS SPEED GRADE
I
0.125ps
DRVDD
0.25ps
0.5ps
1.0ps
2.0ps
SAMPLE
30
100
for f
IN
40
= 7.5 MHz
16 BITS
14 BITS
12 BITS
50
1000
Rev. B | Page 29 of 60
By asserting the PDWN pin high, the AD9271 is placed into
power-down mode. In this state, the device typically dissipates
2 mW. During power-down, the LVDS output drivers are placed
into a high impedance state. The AD9271 returns to normal
operating mode when the PDWN pin is pulled low. This pin is
both 1.8 V and 3.3 V tolerant.
By asserting the STBY pin high, the AD9271 is placed into a
standby mode. In this state, the device typically dissipates
65 mW. During standby, the entire part is powered down except
the internal references. The LVDS output drivers are placed into
a high impedance state. This mode is well suited for applications
that require power savings because it allows the device to be
powered down when not in use and then quickly powered up.
The time to power the device back up is also greatly reduced. The
AD9271 returns to normal operating mode when the STBY pin
is pulled low. This pin is both 1.8 V and 3.3 V tolerant.
In power-down mode, low power dissipation is achieved by
shutting down the reference, reference buffer, PLL, and biasing
networks. The decoupling capacitors on REFT and REFB are
discharged when entering power-down mode and must be
recharged when returning to normal operation. As a result, the
wake-up time is related to the time spent in the power-down
mode: shorter cycles result in proportionally shorter wake-up
times. To restore the device to full operation, approximately
1 ms is required when using the recommended 0.1 μF and 4.7 μF
decoupling capacitors on the REFT and REFB pins and the
0.01 μF decoupling capacitors on the GAIN± pins. Most of this
time is dependent on the gain decoupling; higher value decoupling
capacitors on the GAIN± pins result in longer wake-up times.
There are a number of other power-down options available
when using the SPI port interface. The user can individually
power down each channel or put the entire device into standby
mode. This allows the user to keep the internal PLL powered up
when fast wake-up times are required. The wake-up time is
slightly dependent on gain. To achieve a 1 μs wake-up time
when the device is in standby mode, 0.5 V must be applied to
the GAIN± pins. See the Memory Map section for more details
on using these features.
190
180
170
160
150
140
130
120
110
100
Figure 61. Power per Channel vs. f
0
10
SAMPLING FREQUENCY (MSPS)
25MSPS SPEED GRADE
20
40MSPS SPEED GRADE
50MSPS SPEED GRADE
30
SAMPLE
for f
40
IN
= 7.5 MHz
AD9271
50