AD7294 Analog Devices, AD7294 Datasheet - Page 27

• Manufacturer Part Number: AD7294
• Description: 12-Bit Monitor and Control System with Multichannel ADC, DACs, Temperature Sensor, and Current Sense
• Manufacturer: Analog Devices

Specifications of AD7294

• Resolution (bits): 12bit
• # Chan: 9
• Sample Rate: 200kSPS
• Interface: I²C/Ser 2-Wire,Ser
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (Vref) p-p,2 V p-p,Uni (Vref),Uni (Vref) x 2
• Adc Architecture: SAR
• Pkg Type: CSP

Data Sheet
REGISTER SETTING
The
store conversion results, high and low conversion limits, and
information to configure and control the device.
Each data register has an address to which the address pointer
register points when communicating with it. The command
register is the only register that is a write-only register; the rest
are read/write registers.
ADDRESS POINTER REGISTER
The address pointer register is an 8-bit register, in which the
6 LSBs are used as pointer bits to store an address that points
to one of the
AD7294
REGISTER
ADDRESS
POINTER
AD7294
contains internal registers (see Figure 49) that
Figure 49.
SERIAL BUS INTERFACE
data registers, see Table 9.
AD7294
T
T
REGISTERS × 3
REGISTERS × 3
REGISTERS × 2
POWER-DOWN
CONFIGURATION
REGISTERS × 18
SENSE
SENSE
HYSTERESIS
REGISTERS
SEQUENCE
COMMAND
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
CHANNEL
DATA HIGH /
REGISTER
DATA LOW
RESULT
ALERT
DAC
RESULT
OFFSET
Register Structure
SDA
SCL
Rev. H | Page 27 of 48
Table 9.
Address in Hex
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
40
41
AD7294
Register Address
Registers (R is Read/W is Write)
Command Register (W)
Result Register (R)/DAC
T
T
T
Alert Register A (R/W)
Alert Register B (R/W)
Alert Register C (R/W)
Channel Sequence Register (R/W)
Configuration Register (R/W)
Power-Down Register (R/W)
DATA
DATA
Hysteresis Register V
DATA
DATA
Hysteresis Register V
DATA
DATA
Hysteresis Register V
DATA
DATA
Hysteresis Register V
DATA
DATA
Hysteresis Register I
DATA
DATA
Hysteresis Register I
DATA
DATA
Hysteresis Register T
DATA
DATA
Hysteresis Register T
DATA
DATA
Hysteresis Register T
T
T
Factory Test Mode
Factory Test Mode
SENSE
SENSE
SENSE
SENSE
SENSE
1 Result (R)/DAC
2 Result (R)/DAC
INT Result (R)/DAC
1 Offset Register (R/W)
2 Offset Register (R/W)
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
Register V
Register V
Register, V
Register V
Register I
Register I
Register T
Register T
Register T
Register V
Register V
Register V
Register V
Register I
Register I
Register T
Register T
Register T
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
IN
IN
IN
SENSE
SENSE
SENSE
IN
IN
IN
IN
IN
SENSE
SENSE
0 (R/W)
1 (R/W)
3 (R/W)
0 (R/W)
1 (R/W)
2 (R/W)
2 (R/W)
3 (R/W)
SENSE
SENSE
SENSE
IN
IN
IN
IN
B
C
0 (R/W)
1 (R/W)
2 (R/W)
3 (R/W)
1 (R/W)
2 (R/W)
1 (R/W)
2 (R/W)
1 (R/W)
2 (R/W)
INT (R/W)
Value (W)
Value (W)
1 (R/W)
2 (R/W)
INT (R/W)
A
D
1 (R/W)
2 (R/W)
1 (R/W)
2 (R/W)
INT (R/W)
Value (W)
Value (W)
AD7294