AD7148 Analog Devices, AD7148 Datasheet - Page 44

• Manufacturer Part Number: AD7148
• Manufacturer: Analog Devices

Specifications of AD7148

• Resolution (bits): 16bit
• # Chan: 8
• Sample Rate: 250kSPS
• Interface: I²C/Ser 2-Wire,Ser
• Analog Input Type: SE-Uni
• Ain Range: ± 8 pF (Delta C)
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

AD7148
Table 34. STAGE3 Configuration Registers
Address
0x098
0x099
0x09A
0x09B
0x09C
0x09D
0x09E
0x09F
Table 35. STAGE4 Configuration Registers
Address
0x0A0
0x0A1
0x0A2
0x0A3
0x0A4
0x0A5
0x0A6
0x0A7
Table 36. STAGE5 Configuration Registers
Address
0x0A8
0x0A9
0x0AA
0x0AB
0x0AC
0x0AD
0x0AE
0x0AF
Table 37. STAGE6 Configuration Registers
Address
0x0B0
0x0B1
0x0B2
0x0B3
0x0B4
0x0B5
0x0B6
0x0B7
Data
Bit
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
Data
Bit
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
Data
Bit
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
Data
Bit
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
Default
Value
X
X
X
X
X
X
X
X
Default
Value
X
X
X
X
X
X
X
X
Default
Value
X
X
X
X
X
X
X
X
Default
Value
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Type
Type
Type
Type
Mnemonic
STAGE3_CONNECTION_SETUP[6:0]
STAGE3_CONNECTION_SETUP[7]
STAGE3_AFE_OFFSET
STAGE3_SENSITIVITY
STAGE3_OFFSET_LOW
STAGE3_OFFSET_HIGH
STAGE3_OFFSET_HIGH_CLAMP
STAGE3_OFFSET_LOW_CLAMP
Mnemonic
STAGE4_CONNECTION_SETUP[6:0]
STAGE4_CONNECTION_SETUP[7]
STAGE4_AFE_OFFSET
STAGE4_SENSITIVITY
STAGE4_OFFSET_LOW
STAGE4_OFFSET_HIGH
STAGE4_OFFSET_HIGH_CLAMP
STAGE4_OFFSET_LOW_CLAMP
Name
STAGE5_CONNECTION_SETUP[6:0]
STAGE5_CONNECTION_SETUP[7]
STAGE5_AFE_OFFSET
STAGE5_SENSITIVITY
STAGE5_OFFSET_LOW
STAGE5_OFFSET_HIGH
STAGE5_OFFSET_HIGH_CLAMP
STAGE5_OFFSET_LOW_CLAMP
Mnemonic
STAGE6_CONNECTION_SETUP[6:0]
STAGE6_CONNECTION_SETUP[7]
STAGE6_AFE_OFFSET
STAGE6_SENSITIVITY
STAGE6_OFFSET_LOW
STAGE6_OFFSET_HIGH
STAGE6_OFFSET_HIGH_CLAMP
STAGE6_OFFSET_LOW_CLAMP
Rev. A | Page 44 of 56
STAGE6 CIN[6:0] connection setup (see Table 39)
STAGE6 sensitivity control (see Table 42)
STAGE6 initial offset low value
Description
STAGE6 CIN7 connection setup (see Table 40)
STAGE6 AFE offset control (see Table 41)
STAGE6 initial offset high value
STAGE6 offset high clamp value
STAGE6 offset low clamp value
Description
STAGE3 CIN[6:0] connection setup (see Table 39
STAGE3 CIN7 connection setup (see Table 40)
STAGE3 AFE offset control (see Table 41)
STAGE3 sensitivity control (see Table 42)
STAGE3 initial offset low value
STAGE3 initial offset high value
STAGE3 offset high clamp value
STAGE3 offset low clamp value
Description
STAGE4 CIN[6:0] connection setup (see Table 39)
STAGE4 CIN7 connection setup (see Table 40)
STAGE4 AFE offset control (see Table 41)
STAGE4 sensitivity control (see Table 42)
STAGE4 initial offset low value
STAGE4 initial offset high value
STAGE4 offset high clamp value
STAGE4 offset low clamp value
STAGE5 CIN[6:0] connection setup (see Table 39)
STAGE5 CIN7 connection setup (see Table 40)
STAGE5 AFE offset control (see Table 41)
STAGE5 sensitivity control (see Table 42)
STAGE5 initial offset low value
STAGE5 initial offset high value
STAGE5 offset high clamp value
STAGE5 offset low clamp value
Description