AD7148 Analog Devices, AD7148 Datasheet - Page 13

• Manufacturer Part Number: AD7148
• Manufacturer: Analog Devices

Specifications of AD7148

• Resolution (bits): 16bit
• # Chan: 8
• Sample Rate: 250kSPS
• Interface: I²C/Ser 2-Wire,Ser
• Analog Input Type: SE-Uni
• Ain Range: ± 8 pF (Delta C)
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

CAPACITANCE-TO-DIGITAL CONVERTER
The capacitance-to-digital converter on the AD7148 has a Σ-Δ
architecture with 16-bit resolution. There are eight possible inputs
to the CDC that are connected to the input of the converter
through a switch matrix. The sampling frequency of the CDC
is 250 kHz.
OVERSAMPLING THE CDC OUTPUT
The decimation rate, or oversampling ratio, is determined by
the DECIMATION bits of the PWR_CONTROL register
(Address 0x000[9:8]), as listed in Table 8.
Table 8. CDC Decimation Rate
DECIMATION Bits
00
01
10
11
The decimation process on the AD7148 is an averaging process,
during which a number of samples are taken, and the averaged
result is output. Due to the architecture of the digital filter used,
the number of samples taken (per stage) is equal to 3× the decima-
tion rate. That is, 3 × 256 samples or 3 × 128 samples are averaged
to obtain each stage result.
The decimation process reduces the amount of noise present in
the final CDC result. However, the higher the decimation rate,
the lower the output rate per stage; thus, a trade-off is possible
between a noise-free signal and speed of sampling.
CAPACITANCE SENSOR OFFSET CONTROL
There are two programmable DACs on board the AD7148 to
null the effect of any stray capacitances on the CDC measurement.
These offsets are due to stray capacitance to ground. Best practice
is to ensure that the CDC output for any stage is approximately
equal to midscale (~32,700) when no sensor is active.
Decimation Rate
256
128
64
64
CDC Output Rate
per Stage (ms)
3.072
1.536
0.768
0.768
Rev. A | Page 13 of 56
The simplified block diagram in Figure 20 shows how to apply
the STAGEx_OFFSET registers to null the offsets. The 6-bit
POS_AFE_OFFSET and NEG_AFE_OFFSET bits program the
offset DAC to provide 0.32 pF resolution offset adjustment over a
range of 20 pF. Apply the positive and negative offsets to either the
positive or the negative CDC input using the NEG_AFE_OFFSET
and POS_AFE_OFFSET bits.
This process is required only once during the initial capacitance
sensor characterization.
CONVERSION SEQUENCER
The AD7148 has an on-chip sequencer to implement conversion
control for the input channels. Up to eight conversion stages
can be performed in one sequence. Each of the eight conversion
stages can measure the input from a different sensor. By using
the Bank 2 registers, each stage can be uniquely configured to
support multiple capacitance sensor interface requirements. For
example, a slider sensor can be assigned to STAGE0 through
STAGE7, or a button sensor can be assigned to STAGE0. For each
conversion stage, the input mux that connects the CINx inputs to the
converter can have a unique setting.
CIN
CINx_CONNECTION_SETUP
Figure 20. Analog Front-End Offset Control
BITS
(20pF RANGE)
(20pF RANGE)
–DAC
+DAC
POS_AFE_OFFSET_SWAP BIT
NEG_AFE_OFFSET_SWAP BIT
+
_
16-BIT
CDC
6
6
POS_AFE_OFFSET
NEG_AFE_OFFSET
16
AD7148