AD7148 Analog Devices, AD7148 Datasheet - Page 35

• Manufacturer Part Number: AD7148
• Manufacturer: Analog Devices

Specifications of AD7148

• Resolution (bits): 16bit
• # Chan: 8
• Sample Rate: 250kSPS
• Interface: I²C/Ser 2-Wire,Ser
• Analog Input Type: SE-Uni
• Ain Range: ± 8 pF (Delta C)
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

DETAILED REGISTER DESCRIPTIONS
BANK 1 REGISTERS
All addresses and default values are expressed in hexadecimal format.
Table 17. PWR_CONTROL Register
Address
0x000
Data Bit
[1:0]
[3:2]
[7:4]
[9:8]
[10]
[11]
[12]
[13]
[15:14]
Default
Value
0
0
0
0
0
0
0
0
0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Mnemonic
POWER_MODE
LP_CONV_DELAY
SEQUENCE_STAGE_NUM
DECIMATION
SW_RESET
INT_POL
Unused
CDC_BIAS
Rev. A | Page 35 of 56
Operating modes
Low power mode conversion delay
CDC bias current control
Description
Number of stages in sequence (N + 1)
ADC decimation factor
Software reset control (self-clearing)
Interrupt polarity control
Excitation source control
Set to 0
0 = active low
1 = active high
00 = 200 ms
01 = 400 ms
10 = 600 ms
11 = 800 ms
00 = decimate by 256
01 = decimate by 128
10 = decimate by 64
11 = decimate by 64
1 = resets all registers to default values
0 = enable excitation source to CINx pins
1 = disable excitation source to CINx pins
00 = normal operation
01 = normal operation + 20%
10 = normal operation + 35%
11 = normal operation + 50%
00 = full power mode (normal operation, CDC
conversions approximately every 36 ms)
01 = full shutdown mode (no CDC conversions)
10 = low power mode (automatic wake up operation)
11 = full shutdown mode (no CDC conversions)
0000 = 1 conversion stage in sequence
0001 = 2 conversion stages in sequence
…
Maximum value = 1011 = 12 conversion stages per
sequence
AD7148