AD9230-11 Analog Devices, AD9230-11 Datasheet
AD9230-11
Specifications of AD9230-11
Related parts for AD9230-11
AD9230-11 Summary of contents
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... LVDS (ANSI-644) compatible and support twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing. Fabricated on an advanced CMOS process, the AD9230-11 is available in a 56-lead lead frame chip scale package, specified over the industrial temperature range (−40°C to +85°C). ...
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... AD9230-11 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 DC Specifications ......................................................................... 3 AC Specifications .......................................................................... 4 Digital Specifications ................................................................... 5 Switching Specifications .............................................................. 6 Timing Diagrams .......................................................................... 7 Absolute Maximum Ratings ............................................................ 8 Thermal Resistance ...................................................................... 8 ESD Caution .................................................................................. 8 Pin Configurations and Function Descriptions ........................... 9 Typical Performance Characteristics ........................................... 13 Equivalent Circuits ......................................................................... 15 REVISION HISTORY 10/08— ...
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... MHz sine input at rated sample rate. AVDD DRVDD 4 Single data rate mode; this is the default mode of the AD9230-11. 5 Double data rate mode; user-programmable feature. See the = +85° −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted. ...
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... AD9230-11 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 −40°C, T MIN Table 2. 2 Parameter SNR MHz MHz 170 MHz IN SINAD MHz MHz 170 MHz IN EFFECTIVE NUMBER OF BITS (ENOB MHz MHz 170 MHz IN WORST HARMONIC (SECOND OR THIRD) ...
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... Full −10 Full −10 Full 16 Full Full 0.8 × AVDD Full Full Full Full Full 25°C Full 247 Full 1.125 Twos complement, gray code, or offset binary (default) Rev Page AD9230-11 Typ Max Unit 1 p-p AVDD + 1.6 V AVDD V 3.6 V 0.8 V +10 μA +10 μ kΩ ...
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... AD9230-11 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 −40°C, T MIN Table 4. Parameter CONVERSION RATE Maximum Conversion Rate Minimum Conversion Rate PULSE WIDTH CLK+ Pulse Width High ( CLK+ Pulse Width Low ( OUTPUT (LVDS, SDR MODE) Data Propagation Delay ( Rise Time (t ...
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... N – 7 DATA N – 6 DATA D10 D4 D10 D4 N – – – – MSBs 5 LSBs Figure 3. Double Data Rate Mode Rev Page AD9230- – – – – 5 DATA N – 4 DATA N – ...
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... AD9230-11 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Electrical AVDD to AGND DRVDD to DRGND AGND to DRGND AVDD to DRVDD D0+/D0− through D10+/D10− to DRGND DCO+/DCO− to DRGND OR+/OR− to DGND CLK+ to AGND CLK− to AGND VIN+ to AGND VIN− to AGND SDIO/DCS to DGND PWDN to AGND ...
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... Data Clock Output Input (True Connect. D0 Complement Output Bit (LSB). D0 True Output Bit (LSB). D1 Complement Output Bit. D1 True Output Bit. D2 Complement Output Bit. D2 True Output Bit. Rev Page AD9230-11 42 AVDD 41 AVDD 40 CML 39 AVDD 38 AVDD 37 AVDD 36 VIN– 35 VIN+ 34 AVDD ...
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... AD9230-11 Pin No. Mnemonic 3 D3− 4 D3+ 5 D4− 6 D4+ 9 D5− 10 D5+ 11 D6− 12 D6+ 13 D7− 14 D7+ 15 D8− 16 D8+ 17 D9− 18 D9+ 19 D10− (MSB) 20 D10+ (MSB) 21 OR− 22 OR+ 1 AGND and DRGND should be tied to a common quiet ground plane. ...
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... Data Clock Output Input (True). ND/D5 Complement Output Bit. ND/D5 True Output Bit. D0/D6 Complement Output Bit (LSB). D0/D6 True Output Bit (LSB). D1/D7 Complement Output Bit. D1/D7 True Output Bit. D2/D8 Complement Output Bit. D2/D8 True Output Bit. Rev Page AD9230-11 42 AVDD 41 AVDD 40 CML 39 AVDD 38 AVDD 37 AVDD 36 VIN– 35 VIN+ 34 AVDD ...
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... AD9230-11 Pin No. Mnemonic 3 D3/D9− 4 D3/D9+ 5 D4/D10− (MSB) 6 D4/D10+ (MSB) 9 OR− DNC 21 DNC/(OR−) 22 DNC/(OR+) 1 AGND and DRGND should be tied to a common quiet ground plane. Description D3/D9 Complement Output Bit. D3/D9 True Output Bit. D4/D10 Complement Output Bit (MSB). ...
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... SFDR (dBc) SNR (dB –90 –80 –70 –60 –50 –40 –30 AMPLITUDE (dBFS) Figure 10. SNR/SFDR vs. Input Amplitude; 140.3 MHz 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 –40 –30 –20 – TEMPERATURE (°C) Figure 11. Offset vs. Temperature AD9230-11 350 400 450 ) IN –20 – ...
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... AD9230-11 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 512 1024 OUTPUT CODE Figure 12. DNL 2.5 2.0 1.5 1.0 0.5 0 –0.5 –60 –40 – TEMPERATURE (°C) Figure 13. Gain vs. Temperature 1536 2048 60 80 100 120 Rev Page 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 512 1024 1536 OUTPUT CODE Figure 14 ...
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... AVDD V CML ~1.4V = ~1.4 V) Rev Page AVDD 25kΩ 1kΩ Figure 18. Equivalent CSB Input Circuit DRVDD V+ V– Dx– Dx+ V– V+ Figure 19. LVDS Outputs (Dx+, Dx−, OR+, OR−, DCO+, DCO−) DRVDD 1kΩ SDIO/DCS 25kΩ Figure 20. Equivalent SDIO/DCS Input Circuit AD9230-11 ...
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... At input frequencies in the second Nyquist zone and above, the performance of most amplifiers may not be adequate to achieve the true performance of the AD9230-11. This is especially true in IF undersampling applications where frequencies in the 70 MHz to 100 MHz range are being sampled. For these applications, differen- tial transformer coupling is the recommended input configuration ...
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... This allows a wide range of clock input duty cycles without affecting the perform- ance of the AD9230-11. When the DCS is on, noise and distortion performance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to 0.1µ ...
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... The digital power dissipation does not vary much because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers. By asserting PWDN (Pin 29) high, the AD9230-11 is placed in standby mode or full power-down mode, as determined by the contents of Register 0x08. Reasserting the PWDN pin low returns the AD9230-11 to its normal operational mode ...
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... Configuration Using the SPI section. An output clock signal is provided to assist in capturing data from the AD9230-11. The DCO is used to clock the output data and is equal to the sampling clock (CLK) rate. In single data rate mode (SDR), data is clocked out of the AD9230-11 and must be captured on the rising edge of the DCO ...
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... The pins described in Table 9 comprise the physical interface between the user’s programming device and the serial port of the AD9230-11. All serial pins are inputs, which is an open- drain output and should be tied to an external pull-up or pull-down resistor (suggested value of 10 kΩ). ...
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... D10 to D0 0000 0000 000 0000 0000 000 0000 0000 000 1111 1111 111 1111 1111 111 Rev Page AD9230-11 Twos Complement Mode D10 to D0 1000 0000 000 1000 0000 000 0000 0000 000 0111 1111 111 0111 1111 111 ...
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... The internal update takes place when the transfer bit is set, and the bit autoclears. Bit 5 Bit 4 Bit 3 Bit 2 Soft 1 1 Soft reset reset 8-bit chip ID, Bits[7:0] AD9230-11 = 0x0C 0 Speed grade 200 MSPS Rev Page Default Bit 0 Value ...
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... LVDS LVDS fine adjust: course adjust 3.5 mA (default 2 Rev Page AD9230-11 Default Bit 0 Value Notes/ Bit 1 (LSB) (Hex) Comments 0x00 Determines various generic modes of chip operation. 0 Duty 0x01 cycle stabilizer disabled 1 = enabled ...
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... AD9230-11 Addr. Bit 7 (Hex) Register Name (MSB) Bit 6 0x17 flex_output_delay Output 0 delay enable enable 1 = disable 0x18 flex_vref 0 0 0x2A ovr_config 0 0 Bit 5 Bit 4 Bit 3 Bit 2 0 Output clock delay: 00000 = 0.1 ns 00001 = 0.2 ns 00010 = 0.3 ns … 11101 = 3.0 ns 11110 = 3.1 ns 11111 = 3 Input voltage range setting: 10000 = 0 ...
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... COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2 Figure 34. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ × Body, Very Thin Quad (CP-56-2) Dimensions shown in millimeters Package Description 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] LVDS Evaluation Board Rev Page AD9230-11 0.30 0.23 0.18 PIN 1 56 INDICATOR 1 4.45 EXPOSED 4 ...
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... AD9230-11 NOTES Rev Page ...
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... NOTES Rev Page AD9230-11 ...
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... AD9230-11 NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07101-0-10/08(0) Rev Page ...