AD7147A Analog Devices, AD7147A Datasheet - Page 33

• Manufacturer Part Number: AD7147A
• Manufacturer: Analog Devices

Specifications of AD7147A

• Resolution (bits): 16bit
• # Chan: 13
• Sample Rate: 111SPS
• Interface: I²C/Ser 2-Wire,Ser,SPI
• Analog Input Type: Capacitive
• Ain Range: ± 8 pF (Delta C)
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

SCLK
SCLK
Reading Data
A read transaction begins when the master writes the command
word to the AD7147A with the read/write bit set to 1. The
master then supplies 16 clock pulses per data-word to be read,
and the AD7147A clocks out data from the addressed register
on the SDO line. The first data-word is clocked out on the first
falling edge of SCLK following the command word, as shown in
Figure 50.
SDO
SDI
SDI
CS
CS
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS CAN BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 16-BIT DATA-WORDS.
3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD (ALL 16 BITS MUST BE WRITTEN).
4. CS IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
5. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL WRITE OPERATION:
NOTES
1. SDI BITS ARE LATCHED ON SCLK RISING EDGES. SCLK CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.
2. THE 16-BIT CONTROL WORD MUST BE WRITTEN ON SDI: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS.
3. THE REGISTER DATA IS READ BACK ON THE SDO PIN.
4. X DENOTES DON’T CARE.
5. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT.
6. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK.
7. 16-BIT COMMAND WORD SETTINGS FOR SINGLE READBACK OPERATION:
CW
CW[15:11] = 11100 (ENABLE WORD)
CW[10] = 0 (R/W)
CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (STARTING MSB-JUSTIFIED REGISTER ADDRESS)
15
CW[15:11] = 11100 (ENABLE WORD)
CW[10] = 1 (R/W)
CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB-JUSTIFIED REGISTER ADDRESS)
1
XXX
CW
15
t
ENABLE WORD
CW
2
1
14
t
1
2
ENABLE WORD
XXX
CW
14
CW
13
2
3
t
3
XXX
CW
CW
13
12
4
3
CW
11
XXX
CW
12
5
4
R/W
CW
10
16-BIT COMMAND WORD
XXX
CW
6
11
5
CW
9
7
t
R/W
XXX
CW
4
10
CW
6
8
8
16-BIT COMMAND WORD
XXX
CW
9
STARTING REGISTER ADDRESS
CW
7
7
9
XXX
CW
CW
8
6
10
8
Figure 49. Sequential Register Write SPI Timing
Figure 50. Single Register Readback SPI Timing
XXX
CW
CW
5
7
t
11
5
9
REGISTER ADDRESS
CW
XXX
4
CW
6
12
10
Rev. B | Page 33 of 68
CW
3
XXX
CW
13
5
11
CW
2
14
XXX
CW
4
12
CW
1
15
XXX
CW
3
The AD7147A continues to clock out data on the SDO line if
the master continues to supply the clock signal on SCLK. The
read transaction finishes when the master takes CS high. If the
AD7147A address pointer reaches its maximum value, the
AD7147A repeatedly clocks out data from the addressed register.
The address pointer does not wrap around.
13
CW
0
16
XXX
CW
D15 D14
2
14
17
XXX
DATA FOR STARTING
CW
REGISTER ADDRESS
1
18
15
XXX
CW
0
16
D15
X
17
D1
t
6
31
D14
X
18
D0
32
16-BIT READBACK DATA
D13
X
D15
19
33
D14
REGISTER ADDRESS
34
DATA FOR NEXT
D2
X
30
D1
D1
47
X
AD7147A
t
8
31
D0
t
7
48
D0
X
32
D15
49
XXX