AD9265 Analog Devices, AD9265 Datasheet - Page 31

• Manufacturer Part Number: AD9265
• Description: 16-Bit, 125 MSPS/105 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9265

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 125MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p,1 V p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

Treat the clock input as an analog signal in cases in which
aperture jitter may affect the dynamic range of the AD9265. To
avoid modulating the clock signal with digital noise, separate
power supplies for clock drivers from the ADC output driver
supplies. Low jitter, crystal controlled oscillators make the best
clock sources. If the clock is generated from another type of source
(by gating, dividing, or another method), the output clock should
be retimed by the original clock at the last step.
Refer to AN-501 Application Note, Aperture Uncertainty and
ADC System Performance, and AN-756 Application Note,
Sampled Systems and the Effects of Clock Phase Noise and Jitter
(see www.analog.com) for more information about jitter perfor-
mance as it relates to ADCs.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 81, the power dissipated by the AD9265 is
proportional to its sample rate. In CMOS output mode, the digital
power dissipation is determined primarily by the strength of the
digital drivers and the load on each output bit.
The maximum DRVDD current (IDRVDD) can be
approximately calculated as
where N is the number of output bits (16 data bits plus 1 DCO,
in the case of the AD9265).
This maximum current occurs when every output bit switches on
every clock cycle, that is, a full-scale square wave at the Nyquist
frequency of f
by the average number of output bits switching, which is
determined by the sample rate and the characteristics of the
analog input signal.
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data shown in Figure 81,
Figure 82, and Figure 83 were taken using a 70 MHz analog input
signal with a 5 pF load on each output driver.
0.5
0.4
0.3
0.2
0.1
IDRVDD = VDRVDD × C
0
25
Figure 81. AD9265-125 Power and Current vs. Sample Rate
CLK
/2. In practice, the DRVDD current is established
50
CLOCK FREQUENCY (MSPS)
POWER
IDRVDD
TOTAL
IAVDD
75
LOAD
× f
CLK
× N
100
125
0.20
0.16
0.12
0.08
0.04
0
Rev. A | Page 31 of 44
By asserting PDWN (either through the SPI port or by asserting
the PDWN pin high), the AD9265 is placed in power-down mode.
In this state, the ADC typically dissipates 0.05 mW. During power-
down, the output drivers are placed in a high impedance state.
Asserting the PDWN pin low returns the AD9265 to its normal
operating mode.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering power-
down mode and then must be recharged when returning to normal
operation.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. In addition, when using the SPI
mode, the user can change the function of the external PDWN pin
to either place the part in power-down or standby mode. See the
Memory Map Register Description section for more details.
0.5
0.4
0.3
0.2
0.1
0.5
0.4
0.3
0.2
0.1
0
0
25
25
Figure 82. AD9265-105 Power and Current vs. Sample Rate
Figure 83. AD9265-80 Power and Current vs. Sample Rate
35
35
45
ENCODE FREQUENCY (MSPS)
CLOCK FREQUENCY (MSPS)
45
55
IDRVDD
POWER
TOTAL
IAVDD
POWER
IDRVDD
65
TOTAL
IAVDD
55
75
65
85
95
75
AD9265
105
0.15
0.12
0.09
0.06
0.03
0
0.20
0.16
0.12
0.08
0.04
0