AD7298-1 Analog Devices, AD7298-1 Datasheet - Page 5

• Manufacturer Part Number: AD7298-1
• Description: 8-Channel, 1 MSPS, 10-Bit SAR ADC
• Manufacturer: Analog Devices

Specifications of AD7298-1

• Resolution (bits): 10bit
• # Chan: 8
• Sample Rate: 1MSPS
• Interface: SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref),Uni 1.0V,Uni 1.25,Uni 2.0V,Uni 2.5V
• Adc Architecture: SAR
• Pkg Type: CSP

TIMING SPECIFICATIONS
V
initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
of 1.6 V.
Table 2.
Parameter
t
f
t
t
t
t
t
t
t
t
t
t
t
t
1
SCLK
CONVERT
QUIET
2
3
4
5
6
7
8
9
10
11
POWER-UP
Measured with a load capacitance on DOUT of 15 pF.
1
1
1
1
DD
1
1
= 2.8 V to 3.6 V, V
Limit at T
t
820
50
20
6
10
15
35
28
0.4 × t
0.4 × t
14
16/34
5
4
30
6
2
+ (16 × t
DRIVE
SCLK
SCLK
MIN
SCLK
= 1.65 V to 3.6 V, V
, T
)
MAX
Unit
µs max
ns typ
kHz min
MHz max
ns min
ns min
ns max
ns max
ns max
ns min
ns min
ns min
ns min/ns max
ns min
ns min
ns max
ms max
REF
= 2.5 V internal, T
Test Conditions/Comments
Conversion time
Each ADC channel V
Frequency of external serial clock
Frequency of external serial clock
Minimum quiet time required between the end of the serial read and the start of
the next voltage conversion in repeat and nonrepeat mode.
CS to SCLK setup time
Delay from CS (falling edge) until DOUT three-state disabled
Data access time after SCLK falling edge
V
V
SCLK low pulse width
SCLK high pulse width
SCLK to DOUT valid hold time
SCLK falling edge to DOUT high impedance
DIN setup time prior to SCLK falling edge
DIN hold time after SCLK falling edge
Delay from CS rising edge to DOUT high impedance
Internal reference power-up time from full power-down
DRIVE
DRIVE
Rev. A | Page 5 of 24
= 1.65 V to 3 V
= 3 V to 3.6 V
A
= −40°C to +125°C, unless otherwise noted. Sample tested during
IN0
to V
IN7
, f
SCLK
= 20 MHz
DRIVE
) and timed from a voltage level
AD7298-1