AD7298-1 Analog Devices, AD7298-1 Datasheet - Page 17

• Manufacturer Part Number: AD7298-1
• Description: 8-Channel, 1 MSPS, 10-Bit SAR ADC
• Manufacturer: Analog Devices

Specifications of AD7298-1

• Resolution (bits): 10bit
• # Chan: 8
• Sample Rate: 1MSPS
• Interface: SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref),Uni 1.0V,Uni 1.25,Uni 2.0V,Uni 2.5V
• Adc Architecture: SAR
• Pkg Type: CSP

REPEAT OPERATION
The REPEAT bit in the control register allows the user to select
a sequence of channels on which the AD7298-1 continuously
converts. When the REPEAT bit is set in the control register, the
AD7298-1 continuously cycles through the selected channels in
ascending order, beginning with the lowest channel and converting
all channels selected in the control register. On completion of
the sequence, the AD7298-1 returns to the first selected channel
in the control register and recommences the sequence.
The conversion sequence of the selected channels in the repeat
mode of operation continues until the control register of the
AD7298-1 is reprogrammed. It is not necessary to write to the
control register once a repeat operation is initiated unless a change
in the AD7298-1 configuration is required. The WRITE bit
must be set to zero, or the DIN line tied low to ensure that the
control register is not accidentally overwritten or the automatic
conversion sequence interrupted.
A write to the control register during the repeat mode of operation
resets the cycle even if the selected channels are unchanged.
Thus, the next conversion by the AD7298-1 after a write
operation will be the first selected channel in the sequence.
DOUT
DOUT
SCLK
SCLK
DIN
DIN
CS
CS
1
1
DATA WRITTEN TO CONTROL
REGISTER CH0, CH1, AND CH2
SELECTED: REPEAT = 1
CONVERSION RESULT
CONTROL REGISTER
NO WRITE TO THE
FOR CHANNEL 1
INVALID DATA
10
Figure 25. Configuring a Conversion and Read in Repeat Mode
16
16
1
1
CONVERSION RESULT
CONTROL REGISTER
CONTROL REGISTER
Rev. A | Page 17 of 24
NO WRITE TO THE
NO WRITE TO THE
FOR CHANNEL 2
INVALID DATA
To select a sequence of channels, the associated channel bit
must be set to a logic high state (1) for each analog input whose
conversion is required. For example, if the REPEAT bit = 1, then
CH0, CH1, and CH2 = 1. The V
the first CS falling edge following the write to the control register,
the V
and the V
CS falling edge following the write operation initiates a conversion
on V
operates with one cycle latency, therefore the conversion result
corresponding to each conversion is available one serial read
cycle after the cycle in which the conversion is initiated.
This mode of operation simplifies the operation of the device by
allowing consecutive channels to be converted without having
to reprogram the control register or write to the part on each
serial transfer. Figure 25 illustrates how to set up the AD7298-1
to continuously convert on a particular sequence of channels.
To exit the repeat mode of operation and revert to the traditional
mode of operation of a multichannel ADC, ensure that the
REPEAT bit = 0 on the next serial write.
16
16
IN2
IN1
and has the V
channel is converted on the subsequent CS falling edge,
IN0
conversion result is available for reading. The third
1
1
CONVERSION RESULT
CONVERSION RESULT
CONTROL REGISTER
CONTROL REGISTER
NO WRITE TO THE
NO WRITE TO THE
FOR CHANNEL 0
FOR CHANNEL 0
IN1
result available for reading. The AD7298-1
IN0
analog input is converted on
16
16
AD7298-1