AD7298-1 Analog Devices, AD7298-1 Datasheet - Page 20

• Manufacturer Part Number: AD7298-1
• Description: 8-Channel, 1 MSPS, 10-Bit SAR ADC
• Manufacturer: Analog Devices

Specifications of AD7298-1

• Resolution (bits): 10bit
• # Chan: 8
• Sample Rate: 1MSPS
• Interface: SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref),Uni 1.0V,Uni 1.25,Uni 2.0V,Uni 2.5V
• Adc Architecture: SAR
• Pkg Type: CSP

AD7298-1
SERIAL INTERFACE
Figure 28 shows the detailed timing diagram for the serial interface
to the AD7298-1. The serial clock provides the conversion clock
and controls the transfer of information to and from the AD7298-1
during each conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode
at which point the analog input is sampled and the bus is taken
out of three-state. The conversion is also initiated at this point
and requires 16 SCLK cycles to complete. The track-and-hold
goes back into track mode on the 14
in Figure 28 at Point B. On the 16
rising edge of CS , the DOUT line goes back into three-state.
If the rising edge of CS occurs before 16 SCLKs have elapsed,
the conversion is terminated, the DOUT line goes back into
three-state, and the control register is not updated; otherwise,
DOUT returns to three-state on the 16
Sixteen serial clock cycles are required to perform the conversion
process and to access data from the AD7298-1.
For the AD7298-1, four channel address bits (ADD3 to ADD0)
that identify which channel the conversion result corresponds
to, precede the 10 bits of data (see Table 8).
DOUT
SCLK
DIN
CS
THREE-
STATE
ADD3
t
2
WRITE
t
3
1
ADD2
REPEAT
t
9
th
th
SCLK falling edge or on the
2
SCLK falling edge as shown
ADD1
th
CH0
SCLK falling edge.
3
ADD0
t
CH1
10
Figure 28. Serial Interface Timing Diagram
4
DB9
t
CH2
4
Rev. A | Page 20 of 24
5
DB8
CH3
t
6
When CS goes low, it provides the first address bit to be read in
by the microcontroller or DSP. The remaining data is then clocked
out by subsequent SCLK falling edges, beginning with a second
address bit. Thus, the first falling clock edge on the serial clock
has the first address bit provided for reading and also clocks out
the second address bit. The three remaining address bits and 12
data bits are clocked out by subsequent SCLK falling edges. The
final bit in the data transfer is valid for reading on the 16
edge having been clocked out on the previous (15
In applications with a slower SCLK, it may be possible to read in
data on each SCLK rising edge depending on the SCLK frequency.
The first rising edge of SCLK after the CS falling edge would
have the first address bit provided, and the 15
edge would have last data bit provided.
Writing information to the control register takes place on the
first 16 falling edges of SCLK in a data transfer, assuming the
MSB (that is, the WRITE bit) has been set to 1. The 16-bit word
read from the AD7298-1 always contains four channel address
bits that the conversion result corresponds to, followed by the
12-bit conversion result.
13
EXT_REF
DB0
t
7
B
14
DON’T
CARE
DONTC
15
t
5
t
ACQUISITION
DON’T
CARE
PPD
16
t
8
th
th
rising SCLK
t
) falling edge.
QUIET
THREE-
STATE
th
falling