SAM3N00A Atmel Corporation, SAM3N00A Datasheet - Page 278

• Manufacturer Part Number: SAM3N00A
• Manufacturer: Atmel Corporation

Figure 18-3. Code Read Optimization for FWS = 3
Note:
18.3.2.3
Figure 18-4. Data Read Optimization for FWS = 1
278
Buffer (128bits)
Buffer 1 (128bits)
Buffer 0 (128bits)
ARM Request
Data To ARM
Flash Access
Master Clock
ARM Request
Data To ARM
Flash Access
Master Clock
When FWS is included between 1 and 3, in case of sequential reads, the first access takes (FWS+1) cycles, the other ones only
1 cycle.
(32-bit)
SAM3N
(32-bit)
Data Read Optimization
@Byte 0
XXX
@Byte 0
XXX
XXX
The organization of the Flash in 128 bits (or 64 bits) is associated with two 128-bit (or 64-bit)
prefetch buffers and one 128-bit (or 64-bit) data read buffer, thus providing maximum system
performance. This buffer is added in order to store the requested data plus all the data contained
in the 128-bit (64-bit) aligned data. This speeds up sequential data reads if, for example, FWS is
equal to 1 (see
Note:
Bytes 0-15
XXX
XXX
Bytes 0-15
Bytes 0-3
@ 4
No consecutive data read accesses are mandatory to benefit from this optimization.
XXX
@ 8
4-7
Figure
@4
0-3
18-4).
@ 12
@8
8-11
4-7
Bytes 0-15
@12 @16
Bytes 16-31
8-11
12-15
@ 16
12-15
Bytes 0-15
@20
Bytes 16-31
16-19 20-23
@24
@ 20
16-19
@28 @32
Bytes 32-47
24-27
@ 24
20-23
28-31 32-35
24-27
@ 28
@36 @40
Bytes 16-31
Bytes 16-31
36-39
28-31
@ 32
@44 @48 @52
11011A–ATARM–04-Oct-10
Bytes 48-63
Bytes 32-47
40-43
Bytes 32-47
44-47
@ 36
32-35
48-51