SAM9R64 Atmel Corporation, SAM9R64 Datasheet - Page 129
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SAM9R64
Manufacturer Part Number
SAM9R64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9R64
Flash (kbytes)
0 Kbytes
Pin Count
144
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
49
Ext Interrupts
49
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
5
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
3
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 129 of 290
- Download datasheet (5Mb)
6.6
ARM DDI 0165B
Interlocked MCRR
ARM processor pipeline
LATECANCEL
WDATA[31:0]
RDATA[31:0]
INSTR[31:0]
CHSD[1:0]
CHSE[1:0]
InMREQ
(MCRR)
(MRRC)
PASS
CLK
If the data for an
its first Decode cycle, the ARM9E-S pipeline interlocks for one or more cycles until the
data is available. An example of this is where the register being transferred is the
destination from a preceding
enters the Decode stage of the coprocessor pipeline, and remains there until it can enter
the Execute stage.
Figure 6-6 gives an example of an interlocked MCRR.
MCRR
Copyright © 2000 ARM Limited. All rights reserved.
(interlock)
Decode
GO (ignored)
MCRR
Decode
operation is not available inside the ARM9E-S pipeline during
LDR
GO
Execute
instruction. In this situation the
(GO)
LAST
Execute
Figure 6-6 ARM9E-S interlocked MCRR
(LAST)
Data1 (Rd)
Data1
Ignored
Data2 (Rn)
Memory
ARM9E-S Coprocessor Interface
Data2
MCRR
Write
instruction
6-13
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