SAM9M11 Atmel Corporation, SAM9M11 Datasheet - Page 64

• Manufacturer Part Number: SAM9M11
• Manufacturer: Atmel Corporation

Specifications of SAM9M11

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: Yes
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Dac Resolution (bits): No
• Temp. Sensor: No
• Crypto Engine: AES/DES
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Programmer’s Model
2.8.3
2.8.4
2-18
Leaving an exception
Fast interrupt request
Exceptions are always entered in ARM state. When the processor is in Thumb state and
an exception occurs, the switch to ARM state takes place automatically when the
exception vector address is loaded into the PC. An exception handler might change to
Thumb state but it must return to ARM state to allow the exception handler to terminate
correctly.
When an exception is completed, the exception handler must:
1.
2.
3.
The action of restoring the CPSR from the SPSR automatically resets the T bit to
whatever value it held immediately prior to the exception.
The Fast Interrupt Request (FIQ) exception supports data transfers or channel
processes. In ARM state, FIQ mode has eight banked registers to remove the
requirement for register saving. This minimizes the overhead of context switching.
An FIQ is externally generated by taking the nFIQ input LOW. The input passes into
the core through a synchronizer.
Irrespective of whether exception entry is from ARM state or from Thumb state, an FIQ
handler returns from the interrupt by executing:
FIQ exceptions can be disabled within a privileged mode by setting the CPSR F flag.
When the F flag is clear, the ARM7TDMI processor checks for a LOW level on the
output of the FIQ synchronizer at the end of each instruction.
Move the LR, minus an offset to the PC. The offset varies according to the type
of exception, as shown in Table 2-3 on page 2-16.
Copy the SPSR back to the CPSR.
Clear the interrupt disable flags that were set on entry.
Note
Note
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ARM DDI 0029G