SAM9M11 Atmel Corporation, SAM9M11 Datasheet - Page 167

• Manufacturer Part Number: SAM9M11
• Manufacturer: Atmel Corporation

Specifications of SAM9M11

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: Yes
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Dac Resolution (bits): No
• Temp. Sensor: No
• Crypto Engine: AES/DES
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

6.16
ARM DDI 0029G
ready
not ready
Coprocessor register transfer, load from coprocessor
Cycle
1
2
3
-
1
2
•
b
b+1
b+2
Address
pc+8
pc+12
pc+12
pc+12
pc+8
pc+8
pc+8
pc+8
pc+12
pc+12
pc+12
The busy-wait cycles are similar to those described in Coprocessor data transfer from
memory to coprocessor on page 6-21, but the transfer is limited to one word, and the
ARM7TDMI core puts the data into the destination register in the third cycle. The third
cycle can be merged with the next prefetch cycle into one memory N-cycle as with all
processor register load instructions.
The cycle timings are listed in Table 6-19 where:
•
Coprocessor register transfer operations are not available in Thumb state.
b represents the busy cycles.
Note
MAS
[1:0]
2
2
2
2
2
2
2
2
2
Copyright © 1994-2001. All rights reserved.
Table 6-19 Coprocessor register transfer, load from coprocessor
nRW
0
0
0
0
0
0
0
0
0
Data
(pc+8)
CPdata
-
(pc+8)
-
-
-
CPdata
-
nMREQ
1
1
0
1
1
1
1
1
0
SEQ
1
0
1
0
0
0
1
0
1
nOPC
0
1
1
0
1
1
1
1
1
Instruction Cycle Timings
nCPI
0
1
1
0
0
0
0
1
1
CPA
0
1
-
0
0
0
0
1
-
CPB
0
1
-
1
1
1
0
1
-
6-25