SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 70
SAM9M10
Manufacturer Part Number
SAM9M10
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9M10.pdf
(59 pages)
4.SAM9M10.pdf
(1398 pages)
Specifications of SAM9M10
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
Yes
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Memory Management Unit
3.2.1
3-6
Translation table base
31
The hardware translation process is initiated when the TLB does not contain a
translation for the requested MVA. The Translation Table Base Register (TTBR), CP15
register c2, points to the base address of a table in physical memory that contains section
or page descriptors, or both. The 14 low-order bits [13:0] of the TTBR are
Unpredictable on a read, and the table must reside on a 16KB boundary. Figure 3-1
shows the format of the TTBR.
The translation table has up to 4096 x 32-bit entries, each describing 1MB of virtual
memory. This enables up to 4GB of virtual memory to be addressed.
Figure 3-2 on page 3-7 shows the table walk process.
Copyright © 2001-2003 ARM Limited. All rights reserved.
Translation table base
Figure 3-1 Translation Table Base Register
14 13
ARM DDI0198D
0
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