SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 66
SAM9M10
Manufacturer Part Number
SAM9M10
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9M10.pdf
(59 pages)
4.SAM9M10.pdf
(1398 pages)
Specifications of SAM9M10
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
Yes
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Memory Management Unit
3.1
3-2
About the MMU
The ARM926EJ-S MMU is an ARM architecture v5 MMU. It provides virtual memory
features required by systems operating on platforms such as Symbian OS, WindowsCE,
and Linux. A single set of two-level page tables stored in main memory is used to
control the address translation, permission checks, and memory region attributes for
both data and instruction accesses.
The MMU uses a single unified Translation Lookaside Buffer (TLB) to cache the
information held in the page tables.
To support both sections and pages, there are two levels of address translation. The
MMU puts the translated physical addresses into the MMU Translation Lookaside
Buffer TLB.
The MMU TLB has two parts:
•
•
The main TLB is a two-way, set-associative cache for page table information. It has 32
entries per way for a total of 64 entries. The lockdown TLB is an eight-entry
fully-associative cache that contains locked TLB entries. Locking TLB entries can
ensure that a memory access to a given region never incurs the penalty of a page table
walk. For more details of the TLBs see TLB structure on page 3-31.
The MMU features are:
•
•
•
•
•
•
•
The following subsections are:
•
•
•
Copyright © 2001-2003 ARM Limited. All rights reserved.
the main TLB
the lockdown TLB.
standard ARM architecture v4 and v5 MMU mapping sizes, domains, and access
protection scheme
mapping sizes are 1MB (sections), 64KB (large pages), 4KB (small pages), and
1KB (tiny pages)
access permissions for large pages and small pages can be specified separately for
each quarter of the page (subpage permissions)
hardware page table walks
invalidate entire TLB using CP15 c8
invalidate TLB entry selected by MVA, using CP15 c8
lockdown of TLB entries using CP15 c10.
Access permissions and domains on page 3-3
Translated entries on page 3-3
MMU program accessible registers on page 3-4
ARM DDI0198D
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