SAM9G46 Atmel Corporation, SAM9G46 Datasheet - Page 594
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SAM9G46
Manufacturer Part Number
SAM9G46
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G46.pdf
(58 pages)
Specifications of SAM9G46
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
AES/DES
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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33.7.17
Name:
Address:
Access:
• FRCESTALL: Stall Handshake Request
0 = no effect.
1= If set a STALL answer will be done to the host for the next handshake.
This bit is reset by hardware upon received SETUP.
• TOGGLESQ_STA: Toggle Sequencing
Toggle Sequencing:
Notes:
594
594
SHRT_PCKT
NAK_OUT
These bits are set by hardware to indicate the PID data of the current bank:
Value
– IN endpoint: it indicates the PID Data Toggle that will be used for the next packet sent. This is not relative to
– CONTROL and OUT endpoint:
31
23
15
0
1
2
3
7
TOGGLESQ_STA
the current bank.
1. In OUT transfer, the Toggle information is meaningful only when the current bank is busy (Received OUT Data = 1).
2. These bits are updated for OUT transfer:
3. For High Bandwidth Isochronous Out endpoint, it is recommended to check the UDPHS_EPTSTAx/ERR_TRANS bit to know
4. This field is reset to DATA1 by the UDPHS_EPTCLRSTAx register TOGGLESQ bit, and by UDPHS_EPTCTLDISx (disable
SAM9G35
SAM9G35
UDPHS Endpoint Status Register
-
-
if the toggle sequencing is correct or not.
endpoint).
a new data has been written into the current bank.
the user has just cleared the Received OUT Data bit to switch to the next bank.
UDPHS_EPTSTAx [x=0..6]
0xF803C11C [0], 0xF803C13C [1], 0xF803C15C [2], 0xF803C17C [3], 0xF803C19C [4], 0xF803C1BC [5],
0xF803C1DC [6]
Read-only
Name
DATA0
DATA1
DATA2
MDATA
ERR_FLUSH
NAK_IN/
30
22
14
6
BYTE_COUNT
Description
DATA0
DATA1
Data2 (only for High Bandwidth Isochronous Endpoint)
MData (only for High Bandwidth Isochronous Endpoint)
ERR_CRISO/
ERR_NBTRA
STALL_SNT/
FRCESTALL
29
21
13
5
ERR_FL_ISO
RX_SETUP/
28
20
12
4
–
BYTE_COUNT
TX_PK_RDY/
ERR_TRANS
27
19
11
BUSY_BANK_STA
3
–
TX_COMPLT
26
18
10
2
–
RX_BK_RDY/
KILL_BANK
25
17
CURRENT_BANK/
9
1
–
CONTROL_DIR
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
ERR_OVFLW
24
16
8
0
–
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