SAM9G46 Atmel Corporation, SAM9G46 Datasheet - Page 432
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SAM9G46
Manufacturer Part Number
SAM9G46
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G46.pdf
(58 pages)
Specifications of SAM9G46
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
AES/DES
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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SAM9G35
SAM9G35
After initialization, the DDR2-SDRAM devices are fully functional.
19. A mode Normal command is provided. Program the Normal mode into Mode Register
20. Perform a write access to any DDR2-SDRAM address.
21. Write the refresh rate into the count field in the Refresh Timer register (see
(see
address to acknowledge this command.
(Refresh rate = delay between refresh cycles). The DDR2-SDRAM device requires a
refresh every 15.625 μs or 7.81 μs. With a 133 MHz frequency, the refresh timer count
register must to be set with (15.625*133 MHz) = 2079 i.e. 0x081f or (7.81*133 MHz) =
1039 i.e. 0x040f.
Section 30.7.1 on page
456). Perform a write access to any DDR2-SDRAM
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
page
457).
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