SAM9G35 Atmel Corporation, SAM9G35 Datasheet - Page 51
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SAM9G35
Manufacturer Part Number
SAM9G35
Description
Manufacturer
Atmel Corporation
Specifications of SAM9G35
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
6
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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ARM DDI0198D
Function/operation
Invalidate DCache single entry (Set/Way)
Clean DCache single entry (MVA)
Clean DCache single entry (Set/Way)
Test and clean DCache
Clean and invalidate DCache entry (MVA)
Clean and invalidate DCache entry (Set/Way)
Test, clean, and invalidate DCache
Drain write buffer
Wait for interrupt
31
The MVA format for Rd for the CP15 c7 MCR operations is shown in Figure 2-9. The
Tag, Set, and Word fields define the MVA. For all of the cache operations, Word Should
Be Zero.
The Set/Way format for Rd for the CP15 c7 MCR operations is shown in Figure 2-10
on page 2-24, where A and S are the base-two logarithms of the associativity and the
number of sets. The Set, Way, and Word fields define the format. For all of the cache
operations, Word Should Be Zero.
For a 16KB cache, 4-way set associative, 8-word line, then:
•
•
Copyright © 2001-2003 ARM Limited. All rights reserved.
A = log
S = log
NSETS= cache size in bytes/associativity/line length in bytes:
NSETS= 16384/4/32 = 128
Therefore:
S = log
2
2
2
NSETS where:
128 = 7
associativity = log
Tag
2
4 = 2
Table 2-18 Cache operations c7 (continued)
Data format
Set/Way
MVA
Set/Way
-
MVA
Set/Way
-
SBZ
SBZ
Figure 2-9 Register c7 MVA format
S+5 S+4
Set (= index)
Instruction
Programmer’s Model
5 4
Word
2 1 0
SBZ
2-23
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