SAM9G35 Atmel Corporation, SAM9G35 Datasheet
SAM9G35
Specifications of SAM9G35
Related parts for SAM9G35
SAM9G35 Summary of contents
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... Individually Programmable Open-drain, Pull-up and pull-down resistor, Synchronous Output • Package – 217-ball BGA, pitch 0.8 mm ® Processor running 400 MHz @ 1.0V +/- 10% AT91SAM ARM-based Embedded MPU SAM9G35 Summary NOTE: This is a summary document. The complete document is available on the Atmel website at www.atmel.com. 11053AS–ATARM–27-Jul-11 ...
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... Description The SAM9G35 is a member of the Atmel series of 400 MHz ARM926 embedded MPUs that sup- port high bandwidth communication and advanced user interfaces and are optimized for industrial applications such as building automation, data loggers, POS terminals, alarm systems and medical equipment. ...
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... Block Diagram Figure 2-1. SAM9G35 Block Diagram 11053AS–ATARM–27-Jul-11 PIO PIO SAM9G35 3 ...
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... Fast Interrupt Input PA0-PA31 Parallel IO Controller A PB0-PB18 Parallel IO Controller B PC0-PC31 Parallel IO Controller C PD0-PD21 Parallel IO Controller D SAM9G35 4 gives details on the signal names classified by peripheral. Clocks, Oscillators and PLLs Shutdown, Wakeup Logic ICE and JTAG Reset/Test Debug Unit - DBGU Advanced Interrupt Controller - AIC ...
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... Multimedia Card 0 Slot A Data MCI1_DA0-MCI1_DA3 Multimedia Card 1 Slot A Data 11053AS–ATARM–27-Jul-11 External Bus Interface - EBI Static Memory Controller - SMC NAND Flash Support DDR2/SDRAM/LPDDR Controller High Speed MultiMedia Card Interface - HSMCI0-1 SAM9G35 Type Active Level I/O I/O Output Input Low Output Low ...
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... SPI Serial Clock SPIx_NPCS0 SPI Peripheral Chip Select 0 SPIx_NPCS1-SPIx_NPCS3 SPI Peripheral Chip Select TWDx Two-wire Serial Data TWCKx Two-wire Serial Clock SAM9G35 6 Universal Asynchronous Receiver Transmitter - UARTx Synchronous Serial Controller - SSC Timer/Counter - TCx x=0..5 Serial Peripheral Interface - SPIx Two-Wire Interface -TWIx Type Active Level ...
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... LCDDISP LCD Display Enable 11053AS–ATARM–27-Jul-11 Pulse Width Modulation Controller- PWMC USB Host High Speed Port - UHPHS USB Device High Speed Port - UDPHS RMII Ethernet 10/100 - EMAC LCD Controller - LCDC SAM9G35 Type Active Level Output Analog Analog Analog Analog ...
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... YM_SENSE AD4 Lower Right Channel LR AD5-AD11 7 Analog Inputs ADTRG ADC Trigger ADVREF ADC Reference DIBN Soft Modem Signal DIBP Soft Modem Signal SAM9G35 8 Analog-to-Digital Converter - ADC Soft Modem - SMD Type Active Level Analog Analog Analog Analog Analog Analog Input Analog ...
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... Package and Pinout The SAM9G35 is available in 217-ball BGA package. 4.1 Overview of the 217-ball BGA Package Figure 4-1 Figure 4-1. 4.2 I/O Description Table 4-1. I/O Type GPIO GPIO_CLK GPIO_CLK2 GPIO_ANA EBI EBI_O EBI_CLK RSTJTAG SYSC VBG USBFS USBHS CLOCK DIB 11053AS–ATARM–27-Jul-11 shows the orientation of the 217-ball BGA Package. ...
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... Indicates whether the signal is input or output state. • “PU”/”PD” Indicates whether Pull-Up, Pull-Down or nothing is enabled. SAM9G35 10 SAM9G35 I/O Type Assignment and Frequency I/O Frequency Charge Load Output (MHz) (pF) Current 40 ...
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... MCI0_CDA I/O MCI0_CK I/O MCI0_DA1 I/O MCI0_DA2 I/O MCI0_DA3 I/O TIOA0 I/O TIOA1 I/O TIOA2 I/O TCLK0 I/O TCLK1 I/O TCLK2 I/O TIOB0 I/O TIOB1 I/O TIOB2 I/O TWD0 I/O TWCK0 I/O ERX0 I/O ERX1 SAM9G35 PIO Peripheral B PIO Peripheral C Dir Signal Dir Signal O SPI1_NPCS1 O I SPI0_NPCS2 O O MCI1_DA1 I/O ETX0 I MCI1_DA2 I/O ETX1 I/O MCI1_DA3 I SPI0_NPCS1 O I SPI1_NPCS0 I I/O MCI1_DA0 ...
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... PC18 N3 VDDIOP1 GPIO PC19 K1 VDDIOP1 GPIO PC20 M3 VDDIOP1 GPIO PC21 P3 VDDIOP1 GPIO PC22 J4 VDDIOP1 GPIO PC23 K3 VDDIOP1 GPIO PC24 M2 VDDIOP1 GPIO PC25 SAM9G35 12 Primary Alternate PIO Peripheral A Dir Signal Dir Signal I/O ERXER I/O ERXDV I/O ETXCK I/O EMDIO I/O AD7 I EMDC I/O AD8 I ETXEN I/O AD9 I I/O AD10 ...
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... D20 I/O D21 I/O D22 I/O D23 I/O D24 I/O D25 I/O D26 I/O D27 I/O D28 I/O D29 I/O D30 I/O D31 SAM9G35 PIO Peripheral B PIO Peripheral C Dir Signal Dir Signal O O RTS1 O CTS1 O SCK1 O I PCK1 A20 ...
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... EBI_O A9 G14 VDDIOM EBI_O A10 F15 VDDIOM EBI_O A11 D17 VDDIOM EBI_O A12 C17 VDDIOM EBI_O A13 E16 VDDIOM EBI_O A14 D16 VDDIOM EBI_O A15 C16 VDDIOM EBI_O A16 SAM9G35 14 Primary Alternate PIO Peripheral A Dir Signal Dir Signal I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
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... DFSDP I/O I/O DFSDM I/O I/O DHSDP I/O I/O DHSDM I/O I/O I/O I/O I/O I/O I/O I/O I TDI SAM9G35 PIO Peripheral B PIO Peripheral C Dir Signal Dir Signal Reset State Signal, Dir, PU, Dir PD ...
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... RSTJTAG NRST T11 VDDIOP0 RSTJTAG NTRST A6 VDDBU CLOCK XIN32 A5 VDDBU CLOCK XOUT32 T12 VDDOSC CLOCK XIN U12 VDDOSC CLOCK XOUT SAM9G35 16 Primary Alternate PIO Peripheral A Dir Signal Dir Signal O I PIO Peripheral B PIO Peripheral C Dir Signal Dir Signal 11053AS–ATARM–27-Jul-11 ...
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... Power Considerations 5.1 Power Supplies The SAM9G35 has several types of power supply pins. Table 5-1. SAM9G35 Power Supplies Name Voltage Range, nominal VDDCORE 0.9-1.1V, 1.0V 1.65-1.95V, 1.8V VDDIOM 3.0-3.6V, 3.3V 1.65-1.95V, 1.8V VDDNF 3.0-3.6V, 3.3V VDDIOP0 1.65-3.6V VDDIOP1 1.65-3.6V VDDBU 1.65-3.6V VDDUTMIC 0.9-1.1V, 1.0V VDDUTMII 3.0-3.6V, 3.3V VDDPLLA 0.9-1.1V, 1.0V VDDOSC 1.65-3.6V VDDANA 3.0-3.6V, 3.3V Note: 1. Refer to Table 4-2 for more details. 11053AS–ATARM–27-Jul-11 ...
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... Separate Masters for both instruction and data access providing complete Matrix – Separate Address and Data Buses for both the 32-bit instruction interface and the – On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit SAM9G35 18 each quarter of the page ...
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... APB/AHB Bridge The SAM9G35 product embeds two separated APB/AHB bridges. This architecture enables to make concurrent access on both bridge. Each peripheral can be clocked at a lower speed (MCK divided clock) in order to decrease the current consumption. 6.3 Bus Matrix • 12-layer Matrix, handling requests from 11 masters • ...
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... Master 0 Master 1 Master 2&3 Master 4&5 Master 6 Master 7 Master 8 Master 9 Master 10 6.5 Matrix Slaves The Bus Matrix of the SAM9G35 product manages 9 slaves. Each slave has its own arbiter, allowing a different arbitration per slave. Table 6-2. Slave 0 Slave 1 Slave 2 Slave 3 Slave 4 Slave 5 Slave 6 Slave 7 ...
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... Peripheral Bridge 1 6.7 USB The SAM9G35 features the following USB communication ports: • 2 Hosts (A and B) High Speed (EHCI) and Full Speed (OHCI) • 1 Host (C) Full Speed only (OHCI) • 1 Device High Speed The High Speed USB Host Port A is shared with the High Speed USB Device port and con- nected to the second UTMI transceiver ...
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... The hardware interface numbers are also given in 6-4. Table 6-4. Instance name HSMCI0 SPI0 SPI0 USART0 USART0 USART1 USART1 TWI0 TWI0 TWI2 TWI2 UART0 UART0 SSC SSC SAM9G35 22 DMA Channel Definition DMA Channel HW T/R interface Number RX/ ...
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... Instance name HSMCI1 SPI1 SPI1 SMD SMD TWI1 TWI1 ADC DBGU DBGU UART1 UART1 USART2 USART2 11053AS–ATARM–27-Jul-11 DMA Channel Definition DMA Channel HW T/R interface Number RX/ SAM9G35 Table 23 ...
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... Two Independent Registers: Debug Control Register and Debug Status Register – Test Access Port Accessible through JTAG Protocol – Debug Communications Channel • Debug Unit – Two-pin UART – Debug Communication Channel Interrupt Handling – Chip ID Register • IEEE1149.1 JTAG Boundary-scan on All Digital Pins. SAM9G35 24 11053AS–ATARM–27-Jul-11 ...
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... Memories Figure 7-1. SAM9G35 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 0x0FFF FFFF 0x1000 0000 EBI Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI Chip Select 1 DDR2/LPDDR SDR/LPSDR 0x2FFF FFFF 0x3000 0000 EBI Chip Select 2 0x3FFF FFFF 0x4000 0000 EBI Chip Select 3 ...
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... Embedded Memories 7.2.1 Internal SRAM The SAM9G35 embeds a total of 32 Kbytes of high-speed SRAM. After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0030 0000. After Remap, the SRAM also becomes available at address 0x0. 7.2.2 Internal ROM The SAM9G35 embeds an Internal ROM, which contains the SAM-BA program ...
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... SDRAM Power-up Initialization by Software • CAS Latency Supported • Auto Precharge Command Not Used • SDR-SDRAM with 16-bit Datapath and Eight Columns Not Supported – Clock Frequency Change in Precharge Power-down Mode Not Supported 11053AS–ATARM–27-Jul-11 Average Latency of Transactions) SAM9G35 27 ...
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... System Controller can be addressed from a single pointer by using the stan- dard ARM instruction set, as the Load/Store instruction have an indexing mode of ±4 KBytes. Figure 8-1 Figure 7-1 SAM9G35 28 shows the System Controller block diagram. shows the mapping of the User Interface of the System Controller peripherals. ...
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... Figure 8-1. SAM9G35 System Controller Block Diagram periph_irq[2..30] pit_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset periph_nreset proc_nreset NRST VDDCORE POR VDDBU VDDBU POR backup_nreset SHDN WKUP XIN32 SLOW CLOCK XOUT32 OSC XIN 12MHz MAIN OSC XOUT UPLL PLLA periph_nreset periph_nreset periph_clk[2..3] PA0-PA31 PB0-PB18 ...
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... Chip ID: 0x819A_05A1 • Chip ID Extension: 1 • JTAG ID: 0x05B2_F03F • ARM926 TAP ID: 0x0792_603F 8.2 Backup Section The SAM9G35 features a Backup Section that embeds: • RC Oscillator • Slow Clock Oscillator • Real Time Counter (RTC) • Shutdown Controller • 4 Backup Registers • Slow Clock Control Register (SCKCR) • ...
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... Figure 7-1, the Peripherals are mapped in the upper 256 Mbytes of the address defines the Peripheral Identifiers of the SAM9G35. A peripheral identifier is required Peripheral Identifiers Instance Name Instance Description AIC Advanced Interrupt Controller System Controller Interrupt SYS ...
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... Peripheral Signal Multiplexing on I/O Lines The SAM9G35 features 4 PIO Controllers, PIOA, PIOB, PIOC and PIOD, which multiplex the I/O lines of the peripheral set. Each PIO Controller controls 32 lines, 19 lines, 32 lines and 22 lines respectively for PIOA, PIOB, PIOC and PIOD. Each line can be assigned to one of three peripheral functions ...
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... Asynchronous Mode stop bits in Synchronous Mode – Parity generation and error detection – Framing error detection, overrun error detection 11053AS–ATARM–27-Jul-11 peripherals Sensors and data per chip select SAM9G35 33 ...
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... Two UARTs • Independent receiver and transmitter with a common programmable Baud Rate Generator • Even, Odd, Mark or Space Parity Generation • Parity, Framing and Overrun Error Detection • Automatic Echo, Local Loopback and Remote Loopback Channel Modes SAM9G35 34 11053AS–ATARM–27-Jul-11 ...
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... Compatibility with MMC Plus Specification Version 4.3 • Compatibility with MultiMedia Card Specification Version 4.1 • Compatibility with SD Memory Card Specification Version 2.0 • Compatibility with SDIO Specification Version V2.0. • Compatibility with CE ATA 11053AS–ATARM–27-Jul-11 SAM9G35 2 S, TDM Buses, Magnetic Card Reader, ...) 35 ...
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... External trigger pin – Timer Counter outputs TIOA0 to TIOA2 trigger • Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all • Compare level interrupt for background signal surveillance SAM9G35 36 enabled channels 11053AS–ATARM–27-Jul-11 ...
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... Support physical layer management through MDIO interface • Support Wake On Lan: The receiver supports Wake on LAN by detecting the following events on incoming receive frames: – Magic packet – ARP request to the device IP address – Specific address 1 filter match – Multicast hash filter match 11053AS–ATARM–27-Jul-11 SAM9G35 37 ...
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... Programmable DMA lock transfer support • Transfer Initiation – Support for Software handshaking interface. Memory mapped registers can be used • Interrupt – Programmable Interrupt generation on DMA Transfer completion Block Transfer SAM9G35 38 lists transfer. Writing a stream of data into non-contiguous fields in system memory transfer ...
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... Type I Caller ID (CID) decoding • Sixty-three embedded and upgradeable country profiles • Embedded AT commands • SmartDAA – Extension pick-up detection – Digital line protection – Line reversal detection – Line-in-use detection – Remote hang-up detection – Worldwide compliance 11053AS–ATARM–27-Jul-11 SAM9G35 39 ...
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... Mechanical Overview Figure 11-1. 217-ball BGA Package Drawing SAM9G35 40 11053AS–ATARM–27-Jul-11 ...
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... Device and 217-ball BGA Package Maximum Weight 450 Table 11-2. 217-ball BGA Package Characteristics Moisture Sensitivity Level Table 11-3. Package Reference JEDEC Drawing Reference JESD97 Classification Table 11-4. Soldering Information Ball Land Solder Mask Opening 11053AS–ATARM–27-Jul- MO-205 e1 0.43 mm ± 0.05 0.30 mm ± 0.05 SAM9G35 41 ...
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... SAM9G35 Ordering Information Table 12-1. SAM9G35 Ordering Information Ordering Code AT91SAM9G35-CU SAM9G35 42 Package Package Type BGA217 Green Temperature Operating Range Industrial -40°C to 85°C 11053AS–ATARM–27-Jul-11 ...
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