SAM9G35 Atmel Corporation, SAM9G35 Datasheet - Page 203
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SAM9G35
Manufacturer Part Number
SAM9G35
Description
Manufacturer
Atmel Corporation
Specifications of SAM9G35
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
6
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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ARM DDI0198D
Signal
DRSIZE[3:0]
DRWAIT
DRWBL[3:0]
DRWD[31:0]
INITRAM
IRADDR[17:0]
IRCS
Copyright © 2001-2003 ARM Limited. All rights reserved.
Direction
Input
Input
Output
Output
Input
Output
Output
Function
Data TCM size.
Static configuration input that specifies the physical
size of TCM memories attached.
0000 = absent
0011 = 4KB
0100 = 8KB
…
1010 = 512KB
1011 = 1MB
Values 0001, 0010, and 1100 to 1111 are reserved.
Data TCM wait state input.
If HIGH, the DTCM cannot service the request in
that cycle.
Valid in request cycle and subsequent wait cycles.
Ignored if not a request or wait cycle.
Data TCM write data byte lane indicator.
Valid during request cycles.
For reads, set to b0000
For writes indicates which byte(s) are to be written,
depending on the address and the size of the access
(word, halfword, or byte).
Bits of DRWBL are set only when a write is taking
place, so when DnRW is unset all the bits of
DRWBL are also unset.
Data TCM write data.
Valid during request cycles when DRnRW is 0.
Valid during waited write cycles.
Enables instruction TCM at system reset.
Enables booting from the instruction TCM if
VINITHI is LOW.
Instruction TCM address.
This is the word address for the access. Valid during
request cycles.
Chip select.
Indicates if an access will take place in the following
cycle. Not valid during wait cycles.
Table A-7 TCM interface signals (continued)
Signal Descriptions
A-15
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