SAM9260 Atmel Corporation, SAM9260 Datasheet - Page 106

• Manufacturer Part Number: SAM9260
• Manufacturer: Atmel Corporation

Specifications of SAM9260

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 210 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 7
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Memory Interface
4.11
4.11.1
4.11.2
4-30
Endian effects for data transfers
Writes
Reads
The ARM9E-S supports 32-bit, 16-bit, and 8-bit data memory access sizes. The endian
configuration of the processor, set by CFGBIGEND, affects only nonword transfers
(16-bit and 8-bit transfers).
For data writes by the processor, the write data is duplicated on the data bus. So for a
16-bit data store, one copy of the data appears on the upper half of the write data bus,
WDATA[31:16], and the same data appears on the lower half, WDATA[15:0]. For
8-bit writes four copies are output, one on each byte lane:
•
•
•
•
This considerably eases the memory control logic design and helps overcome any
endian effects.
For data reads, the processor reads a specific part of the read data bus. This is
determined by:
•
•
•
Table 4-13 on page 4-22 shows which bits of the data bus are read for 16-bit reads, and
Table 4-14 on page 4-22 shows which bits are read for 8-bit transfers.
For simplicity of design, 32-bits of data can be read from memory and the processor
ignores any unwanted bits.
WDATA[31:24]
WDATA[23:16]
WDATA[15:8]
WDATA[7:0].
the endian configuration
the size of the transfer
bits 1 and 0 of the data address bus.
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