SAM9260 Atmel Corporation, SAM9260 Datasheet - Page 200
SAM9260
Manufacturer Part Number
SAM9260
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9260.pdf
(802 pages)
5.SAM9260.pdf
(47 pages)
Specifications of SAM9260
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
210 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
7
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9260 PDF datasheet #4
- SAM9260 PDF datasheet #5
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Instruction Cycle Times
8.23
8-40
Cycle
1 register
ready
1 register
not ready
Store coprocessor register (to memory)
1
1
.
n
n+1
IA
pc+3i
pc+3i
pc+3i
pc+3i
pc+3i
The store coprocessor (
coprocessor to memory.
The coprocessor commits to the transfer only when it is ready to write the data. The
coprocessor indicates that it is ready for the transfer to commence by driving CHSD or
CHSE to GO. The ARM9E-S produces addresses and requests data memory writes on
behalf of the coprocessor, which is expected to produce the data at sequential rates. The
coprocessor is responsible for determining the number of words to be transferred. It
indicates this using the CHSD and CHSE signals, setting the appropriate signal to
LAST in the cycle before it is ready to initiate the transfer of the last data word.
An interrupt can cause the ARM9E-S to abandon a busy-waiting coprocessor
instruction (see Busy-waiting and interrupts on page 6-17).
Coprocessor operations are only available in ARM state.
The store coprocessor register cycle timings are shown in Table 8-30.
IREQ
S cycle
I cycle
I cycle
I cycle
S cycle
Note
Copyright © 2000 ARM Limited. All rights reserved.
a
INSTR
(pc+2i)
(pc+3i)
(pc+2i)
-
-
-
(pc+3i)
STC
DA
da
-
-
-
da
) operation transfers one or more words of data from a
DRQ
N cycle
I cycle
I cycle
I cycle
N cycle
Table 8-30 Store coprocessor register cycle timing
b
RDATA
CPData1
-
-
-
CPData1
P
1
1
1
1
1
c
LC
0
0
0
0
0
d
CHSD
LAST
WAIT
ARM DDI 0165B
CHSE
-
WAIT
WAIT
LAST
-
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