SAM7SE32 Atmel Corporation, SAM7SE32 Datasheet - Page 90

• Manufacturer Part Number: SAM7SE32
• Manufacturer: Atmel Corporation

Specifications of SAM7SE32

• Flash (kbytes): 32 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 48 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 88
• Ext Interrupts: 88
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

18.4.2
18.4.3
90
SAM7SE512/256/32
Internal Memory
Area 0
Remap Command
Figure 18-3. Internal Memory Mapping
The first 32 bytes of Internal Memory Area 0 contain the ARM processor exception vectors, in
particular, the Reset Vector at address 0x0.
Before execution of the remap command, the internal ROM or the on-chip Flash is mapped into
Internal Memory Area 0, so that the ARM7TDMI reaches an executable instruction contained in
Flash. A general purpose bit (GPNVM Bit 2) is used to boot either on the ROM (default) or from
the Flash.
Setting the GPNVM Bit 2 selects the boot from the Flash, clearing it selects the boot from the
ROM. Asserting ERASE clears the GPNVM Bit 2 and thus selects the boot from the ROM by
default.
After the remap command, the internal SRAM at address 0x0020 0000 is mapped into Internal
Memory Area 0. The memory mapped into Internal Memory Area 0 is accessible in both its orig-
inal location and at address 0x0.
After execution, the Remap Command causes the Internal SRAM to be accessed through the
Internal Memory Area 0.
As the ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt,
and Fast Interrupt) are mapped from address 0x0 to address 0x20, the Remap Command allows
the user to redefine dynamically these vectors under software control.
The Remap Command is accessible through the Memory Controller User Interface by writing the
MC_RCR (Remap Control Register) RCB field to one.
The Remap Command can be cancelled by writing the MC_RCR RCB field to one, which acts as
a toggling command. This allows easy debug of the user-defined boot sequence by offering a
simple way to put the chip in the same configuration as after a reset.
256M Bytes
0x0000 0000
0x0010 0000
0x0020 0000
0x0030 0000
0x0040 0000
0x000F FFFF
0x001F FFFF
0x002F FFFF
0x003F FFFF
0x0FFF FFFF
Internal Memory Area 1
Internal Memory Area 2
Internal Memory Area 3
Internal Memory Area 0
Undefined Areas
Internal Flash
Internal SRAM
Internal ROM
(Abort)
1 M Bytes
252 M Bytes
1 M Bytes
1 M Bytes
1 M Bytes
6222F–ATARM–14-Jan-11