SAM7SE32 Atmel Corporation, SAM7SE32 Datasheet - Page 170

• Manufacturer Part Number: SAM7SE32
• Manufacturer: Atmel Corporation

Specifications of SAM7SE32

• Flash (kbytes): 32 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 48 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 88
• Ext Interrupts: 88
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

22.6.4.1
22.6.4.2
170
SAM7SE512/256/32
Standard Wait States
External Wait States
Each chip select can be programmed to insert one or more wait states during an access on the
corresponding memory area. This is done by setting the WSEN field in the corresponding
SMC_CSR
grammed in the NWS field in the same register.
Below is the correspondence between the number of standard wait states programmed and the
number of clock cycles during which the NWE pulse is held low:
For each additional wait state programmed, an additional cycle is added.
Figure 22-13. One Standard Wait State Access
Notes:
The NWAIT input pin is used to insert wait states beyond the maximum standard wait states pro-
grammable or in addition to. If NWAIT is asserted low, then the SMC adds a wait state and no
changes are made to the output signals, the internal counters or the state. When NWAIT is de-
asserted, the SMC completes the access sequence.
WARNING: Asserting NWAIT low stops the core’s clock and thus stops program execution.
The input of the NWAIT signal is an asynchronous input. To avoid any metastability problems,
NWAIT is synchronized before using it. This operation results in a two-cycle delay.
NWS must be programmed as a function of synchronization time and delay between NWAIT fall-
ing and control signals falling (NRD/NWE), otherwise SMC will not function correctly.
Note:
WARNING: If NWAIT is asserted during a setup or hold timing, the SMC does not function
correctly.
0 wait states
1 wait state
NWS
1. Early Read Protocol
2. Standard Read Protocol
Where external NWAIT synchronization is equal to 2 cycles.
The minimum value for NWS if NWAIT is used, is 3.
(“SMC Chip Select Registers” on page
≥
Wait Delay from nrd/nwe
A[22:0]
NWE
MCK
NRD
NCS
(1)
1 Wait State Access
(2)
+
external_nwait Synchronization Delay
1/2 clock cycle
1 clock cycle
196). The number of cycles to insert is pro-
6222F–ATARM–14-Jan-11
+
1