SAM7S16 Atmel Corporation, SAM7S16 Datasheet - Page 268

• Manufacturer Part Number: SAM7S16
• Manufacturer: Atmel Corporation

Specifications of SAM7S16

• Flash (kbytes): 16 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 21
• Ext Interrupts: 21
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Debug in Depth
B.16
B-50
The debug status register
The debug status register is 5 bits wide. If it is accessed for a write, with the read/write
bit set, the status bits are written. If it is accessed for a read, with the read/write bit clear,
the status bits are read. The format of the debug status register is shown in Figure B-10.
The function of each bit in this register is as follows:
Bit 4
Bit 3
Bit 2
Bits 1:0
The structure of the debug control and status registers is shown in Figure B-11 on
page B-51.
TBIT
4
Copyright © 1994-2001. All rights reserved.
Enables TBIT to be read. This enables the debugger to determine
the processor state and therefore which instructions to execute.
Enables the debugger to determine if a memory access from the
debug state has completed.
Enables the state of the core interrupt enable signal, IFEN, to be
read. Enables the state of the NMREQ signal from the core,
synchronized to TCK, to be read. This enables the debugger to
determine that a memory access from the debug state has
completed.
Enable the values on the synchronized versions of DBGRQ and
DBGACK to be read.
cgenL
3
IFEN
2
Figure B-10 Debug status register format
DBGRQ
1
ARM DDI 0029G
DBGACK
0