R40008 Atmel Corporation, R40008 Datasheet - Page 63
R40008
Manufacturer Part Number
R40008
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.R40008.pdf
(19 pages)
4.R40008.pdf
(20 pages)
Specifications of R40008
Flash (kbytes)
0 Kbytes
Pin Count
100
Max. Operating Frequency
75 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Speed
No
Usb Interface
No
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
256
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
No
Calibrated Rc Oscillator
No
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2.8.2
ARM DDI 0029G
Exception
or entry
FIQ
IRQ
DABT
RESET
Entering an exception
Return instruction
Not applicable
The ARM7TDMI processor handles an exception as follows:
1.
2.
3.
4.
The ARM7TDMI processor can also set the interrupt disable flags to prevent otherwise
unmanageable nestings of exceptions.
Preserves the address of the next instruction in the appropriate LR.
When the exception entry is from ARM state, the ARM7TDMI processor copies
the address of the next instruction into the LR, current PC+4 or PC+8 depending
on the exception.
When the exception entry is from Thumb state, the ARM7TDMI processor writes
the value of the PC into the LR, offset by a value, current PC+4 or PC+8
depending on the exception, that causes the program to resume from the correct
place on return.
The exception handler does not have to determine the state when entering an
exception. For example, in the case of a SWI,
the next instruction regardless of whether the SWI was executed in ARM or
Thumb state.
Copies the CPSR into the appropriate SPSR.
Forces the CPSR mode bits to a value that depends on the exception.
Forces the PC to fetch the next instruction from the relevant exception vector.
Copyright © 1994-2001. All rights reserved.
Previous state ARM r14_x
Thumb r14_x
PC+4
PC+4
PC+8
-
PC+4
PC+4
PC+8
-
Table 2-3 Exception entry and exit (continued)
Remarks
Where PC is the address of the instruction
that was not executed because the FIQ or
IRQ took priority
Where PC is the address of the Load or Store
instruction that generated the Data Abort
The value saved in r14_svc upon reset is
unpredictable
Programmer’s Model
always returns to
2-17
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