R40008 Atmel Corporation, R40008 Datasheet - Page 60
R40008
Manufacturer Part Number
R40008
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.R40008.pdf
(19 pages)
4.R40008.pdf
(20 pages)
Specifications of R40008
Flash (kbytes)
0 Kbytes
Pin Count
100
Max. Operating Frequency
75 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Speed
No
Usb Interface
No
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
256
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
No
Calibrated Rc Oscillator
No
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Programmer’s Model
2.7.2
2-14
Control bits
All instructions can execute conditionally in ARM state. In Thumb state, only the
Branch instruction can be executed conditionally. For more information about
conditional execution, refer to the ARM Architecture Reference Manual.
The bottom eight bits of a PSR are known collectively as the control bits. They are the:
•
•
•
The control bits change when an exception occurs. When the processor is operating in
a privileged mode, software can manipulate these bits.
Interrupt disable bits
The I and F bits are the interrupt disable bits:
•
•
T bit
The T bit reflects the operating state:
•
•
The operating state is reflected on the external signal TBIT.
Never use an MSR instruction to force a change to the state of the T bit in the CPSR. If
you do this, the processor enters an unpredictable state.
interrupt disable bits
T bit
mode bits.
when the I bit is set, IRQ interrupts are disabled
when the F bit is set, FIQ interrupts are disabled.
when the T bit is set, the processor is executing in Thumb state
when the T bit is clear, the processor executing in ARM state.
Caution
Copyright © 1994-2001. All rights reserved.
ARM DDI 0029G
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