M55800A Atmel Corporation, M55800A Datasheet - Page 16

• Manufacturer Part Number: M55800A
• Manufacturer: Atmel Corporation

Specifications of M55800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 176
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 58
• Ext Interrupts: 58
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 72
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

7.6.1
7.6.2
7.6.3
7.6.4
7.6.5
16
AT91M55800A Summary
Internal Memories
Boot Mode Select
Remap Command
Abort Control
External Bus Interface
In any of these address spaces, the ARM7TDMI operates in Little-Endian mode only.
The AT91M55800A microcontroller integrates an 8-Kbyte primary SRAM bank. This memory
bank is mapped at address 0x0 (after the remap command), allowing ARM7TDMI exception
vectors between 0x0 and 0x20 to be modified by the software. The rest of the bank can be
used for stack allocation (to speed up context saving and restoring), or as data and program
storage for critical algorithms. All internal memory is 32 bits wide and single-clock cycle acces-
sible. Byte (8-bit), half-word (16-bit) or word (32-bit) accesses are supported and are executed
within one cycle. Fetching Thumb or ARM instructions is supported and internal memory can
store twice as many Thumb instructions as ARM ones.
The ARM reset vector is at address 0x0. After the NRST line is released, the ARM7TDMI exe-
cutes the instruction stored at this address. This means that this address must be mapped in
nonvolatile memory after the reset.
The input level on the BMS pin during the last 10 clock cycles before the rising edge of the
NRST selects the type of boot memory (see Table 5).
The BMS pin is multiplexed with the I/O line PB18 that can be programmed after reset like any
standard PIO line.
Table 7-2.
The ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt,
Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to allow these vectors
to be redefined dynamically by the software, the AT91M55800A microcontroller uses a remap
command that enables switching between the boot memory and the internal RAM bank
addresses. The remap command is accessible through the EBI User Interface, by writing one
in RCB of EBI_RCR (Remap Control Register). Performing a remap command is mandatory if
access to the other external devices (connected to chip selects 1 to 7) is required. The remap
operation can only be changed back by an internal reset or an NRST assertion.
The abort signal providing a Data Abort or a Prefetch Abort exception to the ARM7TDMI is
asserted when accessing an undefined address in the EBI address space.
No abort is generated when reading the internal memory or by accessing the internal peripher-
als, whether the address is defined or not.
The External Bus Interface handles the accesses between addresses 0x0040 0000 and
0xFFC0 0000. It generates the signals that control access to the external devices, and can
BMS
1
0
• Internal peripherals in the four highest megabytes
Boot Mode Select
Boot Mode
External 8-bit memory on NCS0
External 16-bit memory on NCS0
1745FS–ATARM–18-Apr-06