M55800A Atmel Corporation, M55800A Datasheet - Page 14

• Manufacturer Part Number: M55800A
• Manufacturer: Atmel Corporation

Specifications of M55800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 176
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 58
• Ext Interrupts: 58
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 72
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

7.3
7.4
7.4.1
7.4.2
14
Master Clock
Reset
AT91M55800A Summary
NRST Pin
NTRST Pin
Master Clock is generated in one of the following ways, depending on programming in the
APMC registers:
The Master Clock (MCK) is also provided as an output of the device on the MCKO pin, whose
state is controlled by the APMC module.
Reset restores the default states of the user interface registers (defined in the user interface of
each peripheral), and forces the ARM7TDMI to perform the next instruction fetch from address
zero. Aside from the program counter, the ARM7TDMI registers do not have defined reset
states.
NRST is active low-level input. It is asserted asynchronously, but exit from reset is synchro-
nized internally to the MCK. At reset, the source of MCK is the Slow Clock (32768 Hz crystal),
and the signal presented on MCK must be active within the specification for a minimum of 10
clock cycles up to the rising edge of NRST, to ensure correct operation.
Test Access Port (TAP) reset functionality is provided through the NTRST signal.
The NTRST control pin initializes the selected TAP controller. The TAP controller involved in
this reset is determined according to the initial logical state applied on the JTAGSEL pin after
the last valid NRST.
In either Boundary Scan or ICE Mode a reset can be performed from the same or different cir-
cuitry, as shown in
be asserted after each power-up. (See the AT91M55800A electrical datasheet, Atmel lit°
1727, for the necessary minimum pulse assertion time.)
Figure 7-1.
Notes:
• From the 32768 Hz low-power oscillator that clocks the RTC
• The on-chip main oscillator, together with a PLL, generate a software-programmable main
clock in the 500 Hz to 33 MHz range. The main oscillator can be bypassed to allow the user
to enter an external clock signal.
Controller
Controller
1. NRST and NTRST handling in Debug Mode during development.
2. NRST and NTRST handling during production.
Reset
Reset
Separate or Common Reset Management
Figure 7-1
NTRST
NRST
AT91M55800A
below. But in all cases, the NTRST like the NRST signal, must
(1)
Controller
Reset
NTRST
NRST
AT91M55800A
1745FS–ATARM–18-Apr-06
(2)